參數資料
型號: MCIMX27
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Multimedia Applications Processor(多媒體應用處理器)
中文描述: 多媒體應用處理器(多媒體應用處理器)
文件頁數: 18/118頁
文件大?。?/td> 1159K
代理商: MCIMX27
i.MX27 Data Sheet, Advance Information, Rev. 0.1
18
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Functional Description and Application Information
2.3.20
Liquid Crystal Display Controller (LCDC)
The Liquid Crystal Display Controller (LCDC) provides display data for external gray-scale or color LCD
panels. The LCDC is capable of supporting black-and-white, gray-scale, passive-matrix color (passive
color or CSTN), and active-matrix color (active color or TFT) LCD panels.
The LCDC provides the following features:
Configurable AHB bus width (32-bit/64-bit).
Support for single (non-split) screen monochrome or color LCD panels and self-refresh type LCD
panels
16 simultaneous gray-scale levels from a palette of 16 for monochrome display
Support for:
— Maximum resolution of 800
×
600
— Passive color panel:
– 4 (mapped to RGB444) / 8 (mapped to RGB444) / 12 (RGB444) bits per pixel (bpp)
— TFT panel:
– 4 (mapped to RGB666) / 8 (mapped to RGB666) / 12 (RGB444) / 16 (RGB565) / 18
(RGB666) bpp
— 16 and 256 colors out of a palette of 4096 colors for 4 bpp and 8 bpp CSTN display,
respectively
— 16 and 256 colors out of a palette of 256 colors for 4 bpp and 8 bpp TFT display, respectively
— True 4096 colors for a 12 bpp display
— True 64K colors for 16 bpp
— True 256K colors for 18 bpp
— 16-bit AUO TFT LCD Panel
— 24-bit AUO TFT LCD Panel
2.3.21
Multi-Master Memory Interface (M3IF)/M3IF-ESDCTL/MDDRC
Interface
The M3IF-ESDCTL/MDDRC interface is optimized and designed to reduce access latency by generating
multiple accesses through the dedicated ESDCTL/MDDRC arbitration (MAB) module, which controls the
access to and from the Enhanced SDRAM/MDDR memory controller. For the other port interfaces, the
M3IF only arbitrates and forwards the master requests received through the Master Port Gasket (MPG)
interface and M3IF Arbitration (M3A) module toward the respective memory controller. The masters that
interface with the M3IF include the ARM Platform, FEC, LCDC, H.264, and the USB. The controllers are
the ESDCTL/MDDRC, PCMCIA, NFC, and WEIM.
2.3.22
Multi-Layer AHB Crossbar Switch (MAX)
The ARM926EJ-S processor’s instruction and data buses—and all alternate bus master
interfaces—arbitrate for resources via a 6
×
34 Multi-Layer AHB Crossbar Switch (MAX). There are six
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