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參數(shù)資料
| 型號(hào)： | MC92604VM |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ETH TXRX DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Common Features
Full-duplex differential data links.
Selectable speed range: 1.25 Gbaud or 0.625 Gbaud.
Low power, approximately less than 1W under typical conditions, while operating in backplane
mode with all transceivers at full speed.
Internal 8B/10B encoder/decoder that may be bypassed.
Source synchronous parallel data input interfaces.
Selectable: Source aligned or source centered timing on the receiver output interfaces.
DDR (RGMII/RTBI), source synchronous, 4-/5-bit optional interfaces.
Parallel interfaces may be either LVTTL or SSTL_2.
Transmit data clock is selectable between per-channel transmit clock or channel ‘A’ transmit clock.
Received data may be clocked to the recovered clock or to the reference clock frequencies.
Unused transceiver channels may be individually disabled.
Drives 50-
or 75- media (100- or 150- differential) for lengths of up to 1.5 meters
board/backplane, or 10 meters of coax.
Tolerates a frequency offset between the transmitter and receiver of +250ppm.
Link inputs have on-chip receiver termination and are “hot swap” compatible.
Differential LVPECL reference clock input with single-ended LVCMOS input option.
Two single-ended buffered reference clock outputs to be used as clock source for associated MAC
interface logic.
Built-in, at speed, self test for production testing and on-board diagnostics.
IEEE Std 1149.1 JTAG boundary scan test support.
Backplane Application Features
Link-to-link synchronization supports aligned, multi-channel, word transfers. Synchronization
mechanism tolerates up to 40 bit-times of link-to-link media delay skew.
Supports three options for word synchronization including disparity based word sync events for
compatibility with legacy transceivers.
Selectable COMMA code group alignment mode enables aligned or unaligned transfers.
Ethernet Friendly Features
Provides the PCS and PMA layers for Ethernet PHYs as specied in IEEE Std 802.3-2000.
MDIO slave interface and registers as dened in IEEE Std 802.3-2000 is fully supported.
Supports rate adaption within IPG for Jumbo frames up to 16K bytes.
General Parameters
The MC92603 and MC92604 are designed in a 0.25
lithography, HiP4 CMOS, 5 layer metal process.
The core logic and high speed serial link I/O require a 1.8 Volt power source while the parallel data
interfaces may be 3.3 V LVTTL or 2.5 V SSTL.
The MC92603 is packaged in a 256 pin MAP Ball Grid Array which has a body size of 17 mm square. The
package for the MC92604 is TBD.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC92604ZT | 功能描述:IC TXRX ETH DUAL GIG 196-MAPBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
| MC92610 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad 3.125 Gbaud SERDES |
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| MC928G | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC929F | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Motorola Inc 功能描述: |
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