
MOTOROLA
MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers
15
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
to uniquely identify each MC92603 channel (00 indicates Channel A, 01 = B, 10 = C, and 11 indicates
Channel D (The least signicant bit for the MC92604 determines channel A or B).
The 2.5 Mhz clock (MD_CLK) is sourced at the MDIO Master (MAC) and is used by each slave MDIO
device. The MC92603/4 are designed as MDIO slave devices.
The MDIO data signal (MD_DATA) is a bidirectional serial signal used to read and write management data
from/to the MDIO Registers.
The specication calls for up to 64 registers to be supported by MDIO. Some registers MUST be included
as a minimum to meet the MDIO specication. These are identied as the “basic” register set. Other
registers are optional and are considered part of the “extended” register set. The MC92603 and MC92604
have four sets of MDIO registers (1 per transceiver). Resisters for address 0 through 6 and 15 through 17,
as dened in the specication, are fully supported. the registers 7 through 14 and 18 through 31 are NOT
supported in the MC92603/4.
Test Features
TheMC92603 and MC92604 supports test modes for in-system BIST testing. They also has a ve terminal
JTAG interface as described in IEEE Std 1149.1.
Each channel of the transceiver may be individually congured for digital loop back where the transmitted
data is looped back to its receiver independent of the receiver’s link inputs. The code groups transmitted are
controlled by the normal transmitter controls. If the transceiver is working properly, the data/control code
groups transmitted are received by the receiver. This allows system logic to use various data sequences to
test the operation of the transceiver.
The loop-back signals are electrically isolated from the output signal pads. Therefore, if the outputs are
shorted, or otherwise restricted, the loop-back signals still operate normally.
The receiver’s link input signals are also electrically isolated during loop back mode, such that their state
does not affect the loop back path.
LBOE controls the state of the link output signals during Loop Back testing. If LBOE is low then
XLINK_x_P/XLINK_x_N are held to low/high respectively. If LBOE is high then data will be present on
the outputs.
The MC92603/4 has an integrated, 23rd order, Pseudo-Noise (PN) pattern generator. Stimulus from this
generator may be used for system testing. The receiver, has a 23rd order signature analyzer that is
synchronized to the incoming PN stream and may be used to count code group mismatch errors relative to
the internal PN reference pattern. This implementation of the 23-bit PN generator and analyzer uses the
polynomial: f = 1 + x5 + x23
The total mismatch error count is presented on the receiver interface signals and is reset to zero when BIST
mode is entered. The count is updated continuously while in BIST mode. The value of this eight-bit error
count is sticky in that the count will not wrap to zero upon overow, but rather, stays at the maximum count
value (11111111). In ALL BERT test modes an error counter is maintained in a MDIO Register for each
specic channel.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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