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參數(shù)資料
| 型號(hào)： | MC92604VM |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ETH TXRX DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類(lèi)型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤(pán) |
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12
MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
In an underrun situation, data must be repeated in order to maintain synchronization between the clock
domains. If ADIE is high the receiver interface repeats the appropriate code groups as described in Table 8
when underrun is imminent.
.
When operating in ‘Word’ mode all congured channels must add/delete IDLEs simultaneously. Therefore
IDLEs must appear in the data stream for all channels simultaneously, so that IDLEs may be repeated or
deleted.
The code group type and timing for rate adaption as described above, is determined by the current context
of the packet stream. The data context is when the transceivers are transmitting MAC frames encapsulated
into code group packets. The code groups in the packet can not be disturbed, therefore, rate adaption is
accomplished in the IPG as previously described. A special case that must be considered in the data context
is Jumbo frames.
Jumbo frames are not supported in the standard but are rather a de facto standard. Jumbo frames violate the
untagged maximum frame size of 1518 code groups and increases the size to 16k code groups. Given a
maximum total frequency offset of 200 ppm, a Jumbo frame could lead to a surplus or decit of 1.67 code
groups for which rate adaption must account. The depth of the receivers elastic buffers may be increased by
conguring JPACK high in order to ensure against starvation in the presence of Jumbo frames. This increase
will lead to longer receiver latency.
Gigabit Ethernet Compatible Operation
The operation of the transceivers in the Ethernet compatibility GMII and TBI modes and the correlation of
the port signal names to the names in the IEEE Std 802.3-2002 specication are listed in the following two
sections.
High
Auto-Negotiate Sequence
Data dropped 16 bytes dropped (/C1/C2/C1/C2/)
High
IDLE Sequence
Data dropped 2 bytes dropped (/I2/)
Table 8. Receiver Reference clock is FASTER than Transmitter Reference Clock
ADIE
COMPAT
Receive Mode
Result
Action Taken
Low
N/A
Underrun
Two bytes of data are lost. First byte reports
underrun, second byte repeats byte prior to
underrun.
High
Low
N/A
Data repeated 2 consecutive IDLEs (K28.5) are repeated.
High
Auto-Negotiate Sequence
Data repeated 16 bytes repeated (/C1/C2/C1/C2/)
High
IDLE Sequence
Data repeated 2 bytes repeated (/I2/)
Table 7. Receiver Reference clock is SLOWER than Transmitter Reference Clock (continued)
ADIE
COMPAT
Receive Mode
Result
Action Taken
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC92604ZT | 功能描述:IC TXRX ETH DUAL GIG 196-MAPBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
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