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參數(shù)資料
| 型號： | MC92604VM |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETH TXRX DUAL GIG 196-MAPBGA |
| 標準包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應商設備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
14
MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
The receiver interface works similar to the backplane 10-bit mode except that word synchronization is not
supported and non-aligned operation is not allowed. Also in this mode the XMIT_x_K input is not required
for the transmitter so it is used to “enable COMMA detect”. The MC92603/4 will always initially perform
even/odd alignment to the rst IDLE (K28.5) code-group encountered. If XMIT_x_K is low it will NOT
realign to any future IDLEs that may appear in the data stream. Data out of the receiver is even/odd aligned
with the two output clocks. IDLEs (K28.5 code groups) are initially aligned with the rising edge of
RECV_x_CLK_B. If “enable COMMA detect” is enabled (XMIT_x_K is high) then a data code group may
be repeated to force this alignment if an IDLE is encountered in an ODD code group.
MDIO
The MDIO (Management Data Input/Output) interface as dened in Clause 22 of IEEE Std 802.3-2002 is
supported by the MC92603and MC92604 Gigabit Ethernet transceivers. Details for protocol and electrical
characteristics are available in the standard.
The MC92603/4 chip MDIO interface consists of 1 enable input, 3 or 4 address inputs, one clock input, and
one bidirectional data signal.
Some users may desire to use the MDIO interface, others may not. If the MDIO interface is to be used then
the MD_ENABLE input must be tied high. The MDIO interface is available whether COMPAT is enabled
or not. On power-up the MC92603/4 will always assume the default conguration dened by the pins of the
device. The conguration can then be changed via the MDIO interface regardless of the application
operating mode. If MDIO is not used (MD_ENABLE is low) The MC92603/4 will operate in the default
conguration.
The MDIO interface is a multidrop serial interface and each part must have a unique PHY Address. In the
MC92603 each channel is addressed separately. The base address to each transceiver must be mod 4. This
address is read from three input ports that must be externally pulled up or pulled down to furnish a unique
address for each part connected to a MDIO bus. The two least signicant bits of the 5 bit address, are used
Table 10. TBI Connection to Standard Ethernet MAC
802.3-2002 Signal
Function
Direction
(relative to
GEt )
GEt Port Name
PMA_TX_CLK
Transmit Clock
Input
XMIT_x_CLK
tx_code_group<9:0> Transmit Data
Input
XMIT_x_ERR,XMIT_x_ENABLE,XMIT_x_[7:0]
EWRAP
Enable Data Wraparound
Input
XMIT_x_LBE
EN_CDET
Enable COMMA detect
Input
XMIT_x_K
COM_DET
Receiver Detected a COMMA
Output
RECV_x_COMMA
rx_code_group<9:0> Receive Data
Output
RECV_x_ERR, RECV_x_DV, RECV_x_[7:0]
-LCK_REF
Enable Lock to Reference
Input
RCCE (normally low, affects all 4 channels)
PMA_RX_CLK<0:1> Receive Clocks (both phases)
Output
RECV_x_CLK, RECV_x_CLK
The following output is available but is not a standard TBI signal
N/A
Receiver Detected an error
Output
RECV_x_K
The following inputs must be externally pulled up/down as indicated
Pull Down
Management Interface Enable
Input
MD_ENABLE
Variable (PUP/PUD)
MDIO PHY Address
Input
MD_ADR[4:2]
Pull Up
Conguration
Input
TBIE
Pull Up
Conguration
Input
BSYNC
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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