MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Hardware Design Considerations
Freescale Semiconductor
84
3.11
Guidelines for PCI Interface Termination
PCI termination if PCI is not used at all.
Option 1
If PCI arbiter is enabled during POR,
— All AD pins will be driven to the stable states after POR. Therefore, all ADs pins can be floating. This includes
PCI_AD[31:0], PCI_C/BE[3:0], and PCI_PAR signals.
— All PCI control pins can be grouped together and tied to OVDD through a single 10-kΩ resistor.
— It is optional to disable PCI block through DEVDISR register after POR reset.
Option 2
If PCI arbiter is disabled during POR,
— All AD pins will be in the input state. Therefore, all ADs pins need to be grouped together and tied to OVDD
through a single (or multiple) 10-k
Ω resistor(s)
— All PCI control pins can be grouped together and tied to OVDD through a single 10-kΩ resistor
— It is optional to disable PCI block through DEVDISR register after POR reset.
3.12
Thermal
This section describes the thermal specifications of the MPC8610.
3.12.1
Thermal Characteristics
Table 62 provides the package thermal characteristics for the MPC8610.
3.12.2
Thermal Management Information
This section provides thermal management information for the flip-chip, plastic ball-grid array (FC_PBGA) package for
air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow,
and thermal interface material. The MPC8610 implements several features designed to assist with thermal management,
including the temperature diode. The temperature diode allows an external device to monitor the die temperature in order to
Table 62. Package Thermal Characteristics1
Characteristic
Symbol
Value
Unit
Notes
Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board
RθJA
24
°C/W
1
Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board
RθJA
18
°C/W
1
Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board
RθJMA
18
°C/W
1
Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board
RθJMA
15
°C/W
1
Junction-to-board thermal resistance
RθJB
10
°C/W
2
Junction-to-case thermal resistance
RθJC
<0.1
°C/W
3
Notes:
1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC
specification for this package.
2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package.
3. Junction-to-case resistance is less than 0.1°C/W because the silicon die is the top of the packaging case..