參數(shù)資料
型號： MC8610VT800GB
廠商： Freescale Semiconductor
文件頁數(shù)： 49/96頁
文件大?。?/td> 0K
描述： MPU E600 CORE 800MHZ 783-PBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 800MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
53
Figure 15 provides the AC test load for PCI.
Figure 26. PCI AC Test Load
Figure 27 shows the PCI input AC timing conditions.
Figure 27. PCI Input AC Timing Measurement Conditions
HRESET high to first FRAME assertion
tPCRHFV
10
—
clocks
8, 11
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing
(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, tSYS, reference (K)
going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R)
went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the
PCI 2.2 Local Bus Specifications.
3. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 × OVDD of the signal in question for
3.3-V PCI signaling levels.
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
system clock period must be kept within the minimum and maximum defined ranges. For values see Section 3.1, “System
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
Specifications.
9. The reset assertion timing requirement for HRESET is 100
μs.
10.Guaranteed by characterization.
11.Guaranteed by design.
12. The timing parameter tPCKHOV is a minimum of 1.5 ns and a maximum of 7.4 ns rather than the minimum of 2 ns and a
maximum of 6 ns in the
PCI 2.2 Local Bus Specifications.
13. The timing parameter tPCIVKH is a minimum of 3.7 ns rather than the minimum of 3 ns in the PCI 2.2 Local Bus Specifications.
14. The timing parameter tPCIXKH is a minimum of 0.8 ns rather than the minimum of 0 ns in the PCI 2.2 Local Bus Specifications.
Table 46. PCI AC Timing Specifications at 66 MHz (continued)
Parameter
Symbol1
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
tPCIVKH
CLK
Input
tPCIXKH
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