參數(shù)資料
型號： MC8610VT800GB
廠商： Freescale Semiconductor
文件頁數(shù)： 27/96頁
文件大小： 0K
描述： MPU E600 CORE 800MHZ 783-PBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 800MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
33
Figure 8 provides the AC test load for the local bus.
Figure 8. Local Bus AC Test Load
Figure 9 to Figure 11 show the local bus signals.
Input setup to local bus clock (except LGTA/LUPWAIT)
tLBIVKH1
4.5
—
ns
3, 4
LGTA/LUPWAIT input setup to local bus clock
tLBIVKL2
4.3
—
ns
3, 4
Input hold from local bus clock (except LGTA/LUPWAIT)
tLBIXKH1
—
0.8
ns
3, 4
LGTA/LUPWAIT input hold from local bus clock
tLBIXKL2
—
0.7
ns
3, 4
LALE output transition to LAD/LDP output transition
(LATCH hold time)
tLBOTOT
0.75
—
ns
5
Local bus clock to output valid (except LAD/LDP and LALE)
tLBKLOV1
—1.1
ns
Local bus clock to data valid for LAD/LDP
tLBKLOV2
—1.2
ns
3
Local bus clock to address valid for LAD, and LALE
tLBKLOV3
—1.2
ns
3
Local bus clock to LALE assertion
tLBKLOV4
—1.4
ns
Output hold from local bus clock (except LAD/LDP and
LALE)
tLBKLOX1
-0.6
—
ns
3
Output hold from local bus clock for LAD/LDP
tLBKLOX2
-0.6
—
ns
3
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
tLBKLOZ1
—2.5
ns
6
Local bus clock to output high Impedance for LAD/LDP
tLBKLOZ2
—2.5
ns
6
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to
the output (O) going invalid (X) or output hold time.
2. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2. Skew number is valid only when LCLK[m] and LCLK[n] have the same load.
3. All signals are measured from BVDD/2 of the edge of local bus clock to 0.4 × BVDD of the signal in question for 3.3-V signaling
levels.
4. Input timings are measured at the pin.
5. The value of tLBOTOT is the measurement of the minimum time between the negation of LALE and any change in LAD.
6. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
7. Guaranteed by design.
Table 26. Local Bus Timing Parameters (BVDD = 3.3 V, 2.5 V and 1.8 V) (continued)
Parameter
Symbol1
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
BVDD/2
RL = 50 Ω
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