參數(shù)資料
型號(hào)： MC8610VT800GB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 51/96頁(yè)
文件大?。?/td> 0K
描述： MPU E600 CORE 800MHZ 783-PBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 800MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
55
of differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak
voltage can also be calculated as VTX-DIFFp-p = 2 * |VOD|.
6.
Differential waveform
The differential waveform is constructed by subtracting the inverting signal (SDn_TX, for example) from the
noninverting signal (SDn_TX, for example) within a differential pair. There is only one signal trace curve in a
differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to
Figure 38 as an example for differential waveform.
7.
Common mode voltage, Vcm
The common mode voltage is equal to one half of the sum of the voltages between each conductor of a balanced
interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSDn_TX + VSDn_TX)/2 = (A + B)/2,
which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the
common mode voltage may often differ from one component’s output to the other’s input. Sometimes, it may be even
different between the receiver input and driver output circuits within the same component. It’s also referred as the DC
offset in some occasion.
Figure 29. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (current mode logic) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 and 2.0 V. Using these values,
the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each
signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential
swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV
and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage
(VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
2.17.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clocks inputs are SDn_REF_CLK and SDn_REF_CLK for PCI Express.
The following sections describe the SerDes reference clock requirements and some application information.
2.17.2.1
SerDes Reference Clock Receiver Characteristics
Figure 30 shows a receiver reference diagram of the SerDes reference clocks.
The supply voltage requirements for XnVDD are specified in Table 2 and Table 3.
Differential Swing, VID or VOD = A – B
A Volts
B Volts
SD
n_TX or
SD
n_RX
SD
n_TX or
SD
n_RX
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)
Vcm = (A + B) / 2
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