參數(shù)資料
型號(hào)： MC7445ARX933LG
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： RISC Microprocessor Hardware Specifications
中文描述： RISC微處理器硬件規(guī)格
文件頁數(shù)： 41/64頁
文件大?。?/td> 1127K
代理商： MC7445ARX933LG
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
41
Package Description
8
Package Description
The following sections provide the package parameters and mechanical dimensions for the CBGA package.
8.1 Package Parameters for the MPC7445, 360 CBGA
The package parameters are as provided in the following list. The package type is 25
×
25 mm, 360-lead ceramic
ball grid array (CBGA).
Package outline
25
×
25 mm
Interconnects
360 (19
×
19 ball array – 1)
Pitch
1.27 mm (50 mil)
Minimum module height
2.72 mm
Maximum module height
3.24 mm
Ball diameter
0.89 mm (35 mil)
V
DD
J9, J11, J13, J15, K10, K12, K14, L9, L11,
L13, L15, M10, M12, M14, N9, N11, N13, N15,
P10, P12, P14
—
—
N/A
Notes:
1. OV
DD
supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls (L3CTL[0:1]);
GV
DD
supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7], L3_ECHO_CLK[0:3],
and L3_CLK[0:1]) and the L3 control signals L3_CNTL[0:1]; and V
DD
supplies power to the processor core and the
PLL (after filtering to become AV
DD
). For actual recommended value of V
in
or supply voltages, see
Table 4
.
2. These input signals are for factory use only and must be pulled up to OV
DD
for normal machine operation.
3. To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8 V) or to HRESET (selects
2.5 V). To program the L3 interface, connect L3VSEL to either GND (selects 1.8 V) or to HRESET (selects 2.5 V)
or to HRESET (selects 1.5 V). If used, pulldown resistors should be less than 250
.
4. Ignored in 60x bus mode.
5. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at
HRESET going high.
6. This signal must be negated during reset, by pull-up to OV
DD
or negation by HRESET (inverse of HRESET), to
ensure proper operation.
7. Internal pull-up on die.
8. These pins require weak pull-up resistors (for example, 4.7 k
) to maintain the control signals in the negated state
after they have been actively negated and released by the MPC7455 and other bus masters.
9. These input signals for factory use only and must be pulled down to GND for normal machine operation.
10.This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
11.Unused address pins must be pulled down to GND.
12.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect
performance.
13.These signals must be pulled down to GND if unused or if the MPC7455 is in 60x bus mode.
14.This signal must be asserted during reset, by pull-down to GND or assertion by HRESET, to ensure proper
operation.
15.Power must be supplied to GV
DD
, even when the L3 interface is disabled or unused.
16.These signals are for factory use only and must be left unconnected for normal machine operation.
Table 16. Pinout Listing for the MPC7455, 483 CBGA Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Select
1
Notes
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