參數(shù)資料
型號： MC68LC060RC66
廠商： Freescale Semiconductor
文件頁數(shù)： 98/128頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 66MHZ 206-PGA
標準包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 66MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應商設備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Memory Management Unit
4-2
M68060 USER’S MANUAL
MOTOROLA
Figure 4-1 illustrates the MMUs contained in the two memory units, one for instructions (sup-
porting instruction prefetches) and one for data (supporting all other accesses). Each MMU
contains a 64-entry ATC, two transparent translation registers (TTRs), and control logic. The
ATCs hold recently used logical to physical address translations, cache mode and protec-
tion information, and whether or not the page has been written. The TTRs are used for defin-
ing the cache modes, enabling protection modes and defining user page attributes for large
regions of untranslated address space. Each MMU also allows enabling a default cache
mode, protection, and user page attributes for address regions not covered by the ATC or
TTRs.
One of the principal functions of the MMU is to provide logical to physical address translation
using translation tables stored in memory. As an MMU receives a request from the corre-
sponding pipe unit, its ATC is searched for the translation, using the upper logical address
bits as a tag. If the translation is resident (or one of the TTRs hit causing transparent trans-
lation), the MMU provides the physical address for the corresponding cache lookup. If the
translation is not in the ATC (and the TTRs miss), then a table search is done using trans-
lation tables stored in memory. When the translation is obtained, it is used for the cache
lookup, and is placed in the ATC for future use. The table search is performed automatically
by the MC68060 using on-chip logic.
Figure 4-1. Memory Management Unit
EXECUTION UNIT
INSTRUCTION
ATC
INSTRUCTION
CACHE
CONTROLLER
DATA
ATC
DATA
CACHE
CONTROLLER
OPERAND DATA BUS
INSTRUCTION
CACHE
DATA
CACHE
FLOATING-
POINT
UNIT
B
U
S
C
O
N
T
R
O
L
E
R
ADDRESS
DATA
INTEGER UNIT
DECODE
DATA AVAILABLE
EA
FETCH
INT
EXECUTE
INSTRUCTION FETCH UNIT
BRANCH
CACHE
INSTRUCTION
FETCH
EARLY
DECODE
INSTRUCTION
BUFFER
EA
CALCULATE
DECODE
EA
FETCH
INT
EXECUTE
EA
FETCH
WRITE-BACK
CONTROL
IA
CALCULATE
EA
CALCULATE
INSTRUCTION MEMORY UNIT
DATA MEMORY UNIT
FP
EXECUTE
pOEP
sOEP
OC
EX
AG
DS
DA
WB
IB
IED
IC
IAG
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