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參數資料
| 型號： | MC68LC060RC66 |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 14/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 66MHZ 206-PGA |
| 標準包裝： | 10 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 66MHz |
| 電壓： | 3.3V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應商設備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤 |
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Caches
MOTOROLA
M68060 USER’S MANUAL
5-11
cache if the corresponding data in memory is modified. Invalidating instruction cache lines
before writing to the corresponding memory lines can prevent this coherency problem, but
only if the data cache line is in writethrough or cache-inhibited mode. A cache coherency
problem could arise if the data cache line is configured as copyback.
To fully support self-modifying code in any situation, it is imperative that a CPUSHA instruc-
tion specifying both caches be executed before the execution of the first self-modified
instruction. The CPUSHA instruction has the effect of ensuring that there is no stale data in
memory, the pipeline is flushed, and instruction prefetches are repeated and taken from
external memory.
5.7 MEMORY ACCESSES FOR CACHE MAINTENANCE
The cache controller in each memory unit performs all maintenance activities that supply
data from the cache to the instruction and operand pipeline units. The activities include
requesting accesses to the bus interface unit for reading new cache lines and writing dirty
cache lines to memory. The following paragraphs describe the memory accesses resulting
from cache fill operations (by both caches) and push operations (by the data cache). Refer
to Section 7 Bus Operation for detailed information about the bus cycles required.
5.7.1 Cache Filling
When a new cache line is required, the cache controller requests a line read from the bus
controller. The bus controller requests a burst read transfer by indicating a line access with
the size signals (SIZ1, SIZ0) and indicates which line in the set is being loaded with the
transfer line number signals (TLN1, TLN0). TLN1 and TLN0 are undefined for the instruction
cache. These pins indicate the appropriate line numbers for cache transfers. Table 5-1 lists
the definition of the TLNx encoding.
The responding device sequentially supplies four long words of data and can assert the
transfer cache inhibit signal (TCI) if the line is not cachable. If the responding device does
not support the burst mode, it should assert the TBI signal for the first long word of the line
access. The bus controller responds by terminating the line access and completes the
remainder of the line read as three, sequential, long-word reads.
Bus controller line accesses implicitly request burst mode operations from external memory.
To operate in the burst mode, the device or external hardware must be able to increment
the low-order address bits as described in Section 7 Bus Operation. The device indicates
its ability to support the burst access by acknowledging the initial long-word transfer with
transfer acknowledge (TA) asserted and TBI negated. This procedure causes the processor
to continue to drive the address and bus control signals and to latch a new data value for
the cache line at the completion of each subsequent cycle (as defined by TA) for a total of
Table 5-1. TLNx Encoding
TLN1
TLN0
Line
0
Zero
0
1
One
1
0
Two
1
Three
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