參數(shù)資料
型號： MC68LC060RC66
廠商： Freescale Semiconductor
文件頁數(shù)： 107/128頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 66MHZ 206-PGA
標準包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 66MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Table of Contents
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M68060 USER’S MANUAL
MOTOROLA
2.3.6
Transfer Size (SIZ1, SIZ0).......................................................................... 2-6
2.3.7
Bus Lock (LOCK)........................................................................................ 2-6
2.3.8
Bus Lock End (LOCKE) .............................................................................. 2-6
2.3.9
Cache Inhibit Out (CIOUT) ......................................................................... 2-7
2.3.10
Byte Select Lines (BS3–BS0) ..................................................................... 2-7
2.4
Master Transfer Control Signals ................................................................... 2-7
2.4.1
Transfer Start (TS)...................................................................................... 2-8
2.4.2
Transfer in Progress (TIP) .......................................................................... 2-8
2.4.3
Starting Termination Acknowledge Signal Sampling (SAS) ....................... 2-8
2.5
Slave Transfer Control Signals ..................................................................... 2-8
2.5.1
Transfer Acknowledge (TA) ........................................................................ 2-8
2.5.2
Transfer Retry Acknowledge (TRA)............................................................ 2-8
2.5.3
Transfer Error Acknowledge (TEA) ............................................................ 2-9
2.5.4
Transfer Burst Inhibit (TBI) ......................................................................... 2-9
2.5.5
Transfer Cache Inhibit (TCI) ....................................................................... 2-9
2.6
Snoop Control (SNOOP) .............................................................................. 2-9
2.7
Arbitration Signals....................................................................................... 2-10
2.7.1
Bus Request (BR)..................................................................................... 2-10
2.7.2
Bus Grant (BG) ......................................................................................... 2-10
2.7.3
Bus Grant Relinquish Control (BGR) ........................................................ 2-10
2.7.4
Bus Tenure Termination (BTT) ................................................................. 2-10
2.7.5
Bus Busy (BB) .......................................................................................... 2-11
2.8
Processor Control Signals .......................................................................... 2-11
2.8.1
Cache Disable (CDIS) .............................................................................. 2-11
2.8.2
MMU Disable (MDIS)................................................................................ 2-12
2.8.3
Reset In (RSTI)......................................................................................... 2-12
2.8.4
Reset Out (RSTO) .................................................................................... 2-12
2.9
Interrupt Control Signals ............................................................................. 2-12
2.9.1
Interrupt Priority Level (IPL2–IPL0) .......................................................... 2-12
2.9.2
Interrupt Pending Status (IPEND) ............................................................ 2-12
2.9.3
Autovector (AVEC) ................................................................................... 2-13
2.10
Status and Clock Signals............................................................................ 2-13
2.10.1
Processor Status (PST4–PST0) ............................................................... 2-13
2.10.2
MC68060 Processor Clock (CLK) ............................................................ 2-14
2.10.3
Clock Enable (CLKEN) ............................................................................. 2-14
2.11
Test Signals ................................................................................................ 2-15
2.11.1
JTAG Enable (JTAG)................................................................................ 2-15
2.11.2
Test Clock (TCK) ...................................................................................... 2-15
2.11.3
Test Mode Select (TMS)........................................................................... 2-15
2.11.4
Test Data In (TDI) ..................................................................................... 2-16
2.11.5
Test Data Out (TDO) ................................................................................ 2-16
2.11.6
Test Reset (TRST) ................................................................................... 2-16
2.12
Thermal Sensing Pins (THERM1, THERM0).............................................. 2-16
2.13
Power Supply Connections......................................................................... 2-16
2.14
Signal Summary ......................................................................................... 2-16
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