參數(shù)資料
型號： MC68LC060RC66
廠商： Freescale Semiconductor
文件頁數(shù)： 118/128頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 66MHZ 206-PGA
標(biāo)準(zhǔn)包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 66MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Table of Contents
MOTOROLA
M68060 USER’S MANUAL
xi
Section 3
Integer Unit
3.1
Integer Unit Execution Pipelines ................................................................... 3-1
3.2
Integer Unit Register Description .................................................................. 3-2
3.2.1
Integer Unit User Programming Model ....................................................... 3-2
3.2.1.1
Data Registers (D7–D0) ........................................................................... 3-2
3.2.1.2
Address Registers (A6–A0) ...................................................................... 3-2
3.2.1.3
User Stack Pointer (A7) ............................................................................ 3-2
3.2.1.4
Program Counter ...................................................................................... 3-3
3.2.1.5
Condition Code Register .......................................................................... 3-3
3.2.2
Integer Unit Supervisor Programming Model.............................................. 3-3
3.2.2.1
Supervisor Stack Pointer .......................................................................... 3-4
3.2.2.2
Status Register ......................................................................................... 3-4
3.2.2.3
Vector Base Register................................................................................ 3-4
3.2.2.4
Alternate Function Code Registers........................................................... 3-5
3.2.2.5
Processor Configuration Register............................................................. 3-5
Section 4
Memory Management Unit
4.1
Memory Management Programming Model.................................................. 4-3
4.1.1
User and Supervisor Root Pointer Registers .............................................. 4-3
4.1.2
Translation Control Register ....................................................................... 4-4
4.1.3
Transparent Translation Registers ............................................................. 4-6
4.2
Logical Address Translation.......................................................................... 4-7
4.2.1
Translation Tables ...................................................................................... 4-7
4.2.2
Descriptors................................................................................................ 4-12
4.2.2.1
Table Descriptors.................................................................................... 4-12
4.2.2.2
Page Descriptors .................................................................................... 4-12
4.2.2.3
Descriptor Field Definitions..................................................................... 4-13
4.2.3
Translation Table Example ....................................................................... 4-15
4.2.4
Variations in Translation Table Structure.................................................. 4-16
4.2.4.1
Indirect Action ......................................................................................... 4-16
4.2.4.2
Table Sharing Between Tasks................................................................ 4-17
4.2.4.3
Table Paging .......................................................................................... 4-17
4.2.4.4
Dynamically Allocated Tables................................................................. 4-17
4.2.5
Table Search Accesses ............................................................................ 4-19
4.2.6
Address Translation Protection................................................................. 4-20
4.2.6.1
Supervisor and User Translation Tables ................................................ 4-21
4.2.6.2
Supervisor Only ...................................................................................... 4-22
4.2.6.3
Write Protect ........................................................................................... 4-22
4.3
Address Translation Caches....................................................................... 4-24
4.4
Transparent Translation.............................................................................. 4-27
4.5
Address Translation Summary.................................................................... 4-28
4.6
RSTI and MDIS Effect on the MMU ............................................................ 4-28
4.6.1
Effect of RSTI on the MMUs ..................................................................... 4-28
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