參數(shù)資料
型號(hào): MC68L11F1CFN3
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 5/174頁(yè)
文件大小: 981K
代理商: MC68L11F1CFN3
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MOTOROLA
SERIAL PERIPHERAL INTERFACE
MC68HC11F1
8-4
TECHNICAL DATA
8.3.1 Master In Slave Out
MISO is one of two unidirectional serial data signals. It is an input to a master device
and an output from a slave device. The MISO line of a slave device is placed in the
high-impedance state if the slave device is not selected.
8.3.2 Master Out Slave In
The MOSI line is the second of the two unidirectional serial data signals. It is an output
from a master device and an input to a slave device. The master device places data
on the MOSI line a half-cycle before the clock edge that the slave device uses to latch
the data.
8.3.3 Serial Clock
SCK, an input to a slave device, is generated by the master device and synchronizes
data movement in and out of the device through the MOSI and MISO lines. Master and
slave devices are capable of exchanging a byte of information during a sequence of
eight clock cycles.
There are four possible timing relationships that can be chosen by using control bits
CPOL and CPHA in the serial peripheral control register (SPCR). Both master and
slave devices must operate with the same timing. The SPI clock rate select bits,
SPR[1:0], in the SPCR of the master device, select the clock rate. In a slave device,
SPR[1:0] have no effect on the operation of the SPI.
8.3.4 Slave Select
The slave select (SS) input of a slave device must be externally asserted before a
master device can exchange data with the slave device. SS must be low before data
transactions and must stay low for the duration of the transaction.
The SS line of the master must be held high. If it goes low, a mode fault error flag
(MODF) is set in the serial peripheral status register (SPSR). To disable the mode fault
circuit, write a one in bit 5 of the port D data direction register. This sets the SS pin to
act as a general-purpose output rather than the dedicated input to the slave select cir-
cuit, thus inhibiting the mode fault flag. The other three lines are dedicated to the SPI
whenever the serial peripheral interface is on.
The state of the master and slave CPHA bits affects the operation of SS. CPHA set-
tings should be identical for master and slave. When CPHA = 0, the shift clock is the
OR of SS with SCK. In this clock phase mode, SS must go high between successive
characters in an SPI message. When CPHA = 1, SS can be left low between succes-
sive SPI characters. In cases where there is only one SPI slave MCU, its SS line can
be tied to Vss as long as only CPHA = 1 clock mode is used.
8.4 SPI System Errors
Two system errors can be detected by the SPI system. The first type of error arises in
a multiple-master system when more than one SPI device simultaneously tries to be
a master. This error is called a mode fault. The second type of error, write collision,
indicates that an attempt was made to write data to the SPDR while a transfer was in
progress.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68L11F1CFNE3 功能描述:8位微控制器 -MCU 8B MCU 1KRAM 512BYTES RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MC68L11K1FN2R2 制造商:Motorola Inc 功能描述:
MC68L11K1FUE2 功能描述:8位微控制器 -MCU 8B MCU L-VOLTAGE-EPP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MC68L711E9FN2 制造商:Rochester Electronics LLC 功能描述:- Bulk
MC68L711E9FNE2 功能描述:8位微控制器 -MCU 8B MCU LO VOLTAGE RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT