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參數(shù)資料
| 型號： | MC68L11F1CFN3 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, EEPROM, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 135/174頁 |
| 文件大?。?/td> | 981K |
| 代理商： | MC68L11F1CFN3 |
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MC68HC11F1
RESETS AND INTERRUPTS
MOTOROLA
TECHNICAL DATA
5-1
SECTION 5 RESETS AND INTERRUPTS
Resets and interrupt operations load the program counter with a vector that points to
a new location from which instructions are to be fetched. A reset causes the internal
control registers to be initialized to a known state. The program counter is loaded with
a known starting address and execution of instructions begins. An interrupt temporarily
suspends normal program execution while an interrupt service routine is being execut-
ed. After an interrupt has been serviced, the main program resumes as if there had
been no interruption.
5.1 Resets
There are four possible sources of reset. Power-on reset (POR) and external reset
share the normal reset vector. The computer operating properly (COP) reset and the
clock monitor reset each has its own vector.
5.1.1 Power-On Reset
A positive transition on VDD generates a power-on reset (POR), which is used only for
power-up conditions. POR cannot be used to detect drops in power supply voltages.
A 4064 tcyc (internal clock cycle) delay after the oscillator becomes active allows the
clock generator to stabilize. If RESET is at logical zero at the end of 4064 tcyc, the CPU
remains in the reset condition until RESET goes to logical one.
It is important to protect the MCU during power transitions. To protect data in EE-
PROM, M68HC11 systems need an external circuit that holds the RESET pin low
whenever VDD is below the minimum operating level. This external voltage level de-
tector, or other external reset circuits, are the usual source of reset in a system. The
POR circuit only initializes internal circuitry during cold starts. Refer to Figure 2–3.
5.1.2 External Reset (RESET)
The CPU distinguishes between internal and external reset conditions by sensing
whether the reset pin rises to a logic one in less than two E-clock cycles after an inter-
nal device releases reset. When a reset condition is sensed, the RESET pin is driven
low by an internal device for four E-clock cycles, then released. Two E-clock cycles
later it is sampled. If the pin is still held low, the CPU assumes that an external reset
has occurred. If the pin is high, it indicates that the reset was initiated internally by ei-
ther the COP system or the clock monitor. It is not advisable to connect an external
resistor capacitor (RC) power-up delay circuit to the reset pin of M68HC11 devices be-
cause the circuit charge time constant can cause the device to misinterpret the type of
reset that occurred.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC68L11F1CFNE3 | 功能描述:8位微控制器 -MCU 8B MCU 1KRAM 512BYTES RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| MC68L11K1FN2R2 | 制造商:Motorola Inc 功能描述: |
| MC68L11K1FUE2 | 功能描述:8位微控制器 -MCU 8B MCU L-VOLTAGE-EPP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| MC68L711E9FN2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68L711E9FNE2 | 功能描述:8位微控制器 -MCU 8B MCU LO VOLTAGE RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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