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參數(shù)資料
| 型號： | MC68HC705L1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 38/102頁 |
| 文件大?。?/td> | 632K |
| 代理商： | MC68HC705L1B |
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MOTOROLA
5-4
MC68HC05L1
PROGRAMMABLE TIMER
5
5.2
Input Capture
‘Input Capture’ is a technique whereby an external signal (connected to TCAP1 or TCAP2 pin) is
used to trigger a read of the free-running counter. In this way it is possible to relate the timing of
an external signal to the internal counter value, and hence to elapsed time.
There are two input capture registers: Input Capture register 1 (ICR1) and Input Capture register 2
(ICR2).
The same input capture interrupt enable bit (ICIE) is used for the two input captures.
5.2.1
Input Capture Register 1 (ICR1)
The two 8-bit registers that make up the 16-bit Input Capture register 1 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit senses
a valid transition at pin TCAP1. The level transition that triggers the counter transfer is dened by
the input edge bit (IEDG1). When an input capture 1 occurs, the corresponding ag ICF1 in TSR
is set. An interrupt can also accompany an input capture 1 provided the ICIE bit in the TCR is set.
The 8 most signicant bits are stored in the Input Capture High 1 register at $14, the 8 least
signicant bits in the Input Capture Low 1 register at $15.
The results obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. The delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the Input
Capture register 1 on each valid signal transition whether the input capture 1 ag (ICF1) is set or
clear. The Input Capture register 1 always contains the free-running counter value that
corresponds to the most recent input capture 1. After a read of the Input Capture 1 register MSB
($14), the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes
the time used in the input capture software routine and its interaction with the main program to
determine the minimum pulse period. A read of the Input Capture 1 register LSB ($15) does not
inhibit the free-running counter transfer since the two actions occur on opposite edges of the
internal bus clock.
Reset does not affect the contents of the Input Capture 1 register, except when exiting Stop mode.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Input capture high 1
$0014
unaffected
Input capture low 1
$0015
unaffected
TPG
38
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