參數(shù)資料
型號(hào)： MC68HC705L1B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝： SDIP-56
文件頁(yè)數(shù)： 27/102頁(yè)
文件大?。?/td> 632K
代理商： MC68HC705L1B
MOTOROLA
4-2
MC68HC05L1
RESETS AND INTERRUPTS
4
Table 4-1 Reset Action on Internal Circuit
DEFAULT CONDITIONS AFTER RESET
1
Timer prescaler reset to zero state
2
Timer counter congures to $FFFC
3
Timer output compare (OCF1 and OCF2) bits reset to zero
4
All timer interrupt enable bits cleared (ICIE, OCIE, and TOIE) to disable timer interrupt
5
Timer OLVL1 and OLVL2 bits are cleared
6
All data direction registers cleared to zero (I/O ports set to input)
7
Congure stack pointer to $00FF
8
Force internal address bus to restart vector ($1FFE-$1FFF)
9
Set I bit in the condition code register to a logic one
10
Clear STOP latch
11
Clear external interrupt latch
12
Clear WAIT latch
13
All bits in address $09 and bits 4 to 7 in $0A are cleared; bits 0 and 1 in $0A are set
14
Bits 3 to 7 in $0B are cleared
Listed numbers do not represent order of occurrence.
Figure 4-1 Power-On Reset and RESET Timing
VDD
OSC1 PIN1
INTERNAL
CLOCK2
INTERNAL
ADDRESS
BUS2
INTERNAL
DATA
BUS2
RESET
1FFE
1FFF
NEW PC
1FFE
1FFF
tVDDR
VDD THRESHOLD (TYPICALLY 1-2V)
4064 tcyc
toxov
tcyc
3
NEW
PCH
NEW
PCL
OP
CODE
tRL=1.5tCYC
PCH
PCL
OP
CODE
NEW PC
NOTES:
1. OSC1 is not meant to represent frequency. It is only used to represent time.
2. Internal clock, internal address bus, and internal data bus signals are not available externally.
3. Next rising edge of internal clock after rising edge of RESET initiates reset sequence.
TPG
28
相關(guān)PDF資料
PDF描述
MC68HC05L1FU 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64
MC68HC05L1B 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
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