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參數(shù)資料
| 型號： | MC68HC705L1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 18/102頁 |
| 文件大?。?/td> | 632K |
| 代理商： | MC68HC705L1B |
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MOTOROLA
2-4
MC68HC05L1
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
2
2.2
INPUT/OUTPUT PORTS
2.2.1
Parallel Ports
Port A, B, and E may be programmed as an input or an output under software control. The
direction of the pins is determined by the state of corresponding bit in the port data direction
register (DDR). Each 8-bit port has an associated 8-bit data direction register. Any port A, B, or E
pin is congured as an output if its corresponding DDR bit is set to a logic one. A pin is congured
as an input if its corresponding DDR bit is cleared to a logic zero. At power-on or reset, all DDRs
are cleared, which congure all port A, B, and E pins as inputs. The data direction registers are
capable of being written to or read by the processor. Refer to Figure 2-3 and Table 2-1. During the
programmed output state, a read of the data register actually reads the value of the output data
latch and not the I/O pin.
2.2.2
Fixed Ports
Port C is an 8-bit xed input port that is shared with 6 analog inputs and 2 voltage references of
the ADC. PC0-PC5 will be congured as 6 analog input when the ADON bit of the ADC Status and
Control register (bit5 of address $09) is set. PC6 and PC7 will be congured as VRH and VRL
correspondingly. At power-on or reset, port C defaults to an input port.
Port D is a four bit port, with PD0 and PD1 are input only, and PD2 and PD3 are output only. PD0
and PD1 are shared with TCAP1 and TCAP2 respectively. PD2 and PD3 are shared with TCMP1
and TCMP2 respectively.
Table 2-1 I/O Pin Functions
R/W
DDR
I/O Pin Function
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
The I/O pin is in an output mode. The output data latch is read.
TPG
20
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