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| 型號(hào)： | MC68HC05L16CFU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 73/146頁 |
| 文件大?。?/td> | 852K |
| 代理商： | MC68HC05L16CFU |
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MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
32
Freescale Semiconductor
2.4.3 Open-Drain Output Control Register 1
DWOMH — Port D Open-Drain Mode (H)
When this bit is set, the upper four bits of port D are configured as open-drain outputs if these bits are
selected as port D output by the PDH bit in the LCDCR. This bit is cleared on reset.
DWOML — Port D Open-Drain Mode (L)
When this bit is set, the lower three bits of port D are configured as open-drain outputs if the
corresponding BPx pin is not used by the LCD driver. This bit is cleared on reset.
EWOMH — Port E Open-Drain Mode (H)
When this bit is set, the upper four bits of port E (that are configured as I/O output by the PEH bit in
the LCDCR) are configured as open-drain outputs. This bit is cleared on reset.
EWOML — Port E Open-Drain Mode (L)
When this bit is set, the lower four bits of port E (that are configured as I/O output by the PEL bit in the
LCDCR) are configured as open-drain outputs. This bit is cleared on reset.
Bits 3 and 2 — Reserved
These bits are not used and always return to logic 0.
AWOMH — Port A Open-Drain Mode (H)
When this bit is set, the upper four bits of port A that are configured as output (corresponding to the
DDRA bit set) become open-drain outputs. This bit is cleared on reset.
AWOML — Port E Open-Drain Mode (L)
When this bit is set, the lower four bits of port A that are configured as output (corresponding DDRA
bit set) become open-drain outputs. This bit is cleared on reset.
2.4.4 Open-Drain Output Control Register 2
Bits 7 and 6 — Reserved
These bits are not used and always read as logic 1. When configured as output, PC6 and PC7 are
always open drain.
Address:
Option Map — $000A
Bit 7
654321
Bit 0
Read:
DWOMH
DWOML
EWOMH
EWOML
0
AWOMH
AWOML
Write:
Reset:
00000000
Figure 2-7. Open-Drain Output Control Register 1 (WOM1)
Address:
Option Map — $000B
Bit 7
654321
Bit 0
Read:
1
CWOM5
CWOM4
CWOM3
CWOM2
CWOM1
CWOM0
Write:
Reset:
11000000
Figure 2-8. Open-Drain Output Control Register 2 (WOM2)
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