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參數(shù)資料
| 型號： | MC68HC05L16CFU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 113/146頁 |
| 文件大小： | 852K |
| 代理商： | MC68HC05L16CFU |
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MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
69
Chapter 8
Simple Serial Peripheral Interface (SSPI)
8.1 Introduction
The simple serial peripheral interface (SSPI) of the MC68HC05L16 is a master/slave synchronous serial
communication module.
SSPI uses a 3-wire protocol: data input, data output, and serial clock. In this format, the clock is not being
included in the data stream and must be provided as a separate signal.
When the SSPI is enabled (SPE = 1), bits 0–2 of port C become SDI (serial data in), SDO (serial data
out), and SCK (serial clocK) pins. The corresponding DDRC bit does not change the direction of the pin.
The MSTR bit decides the SSPI operation mode. The SCK pin is configured as output in master mode
and configured as input in slave mode.
The DORD bit in the serial peripheral control register (SPCR) selects the data transmission order. When
DORD is set, the least significant bit (LSB) of serial data is shifted out/in first. When the DORD is clear,
serial data is shifted from/to the most significant bit (MSB).
Master serial clock speed is selected by the SPR bit in the SPCR. An interrupt may be generated by the
completion of a transfer.
8.2 Features
Features of the SSPI are:
Full-duplex, 3-wire synchronous transfers
Master or slave operation
Programmable data transmission order, LSB or MSB first
1.05-MHz (maximum) transmission bit frequency at 2.1-MHz CPU bus frequency at 5 Vdc
Two programmable transmission bit rates
End-of-transmission interrupt flag
Wakeup from stop mode (slave mode only)
8.3 Functional Descriptions
In master mode, the clock start logic is triggered by the CPU (detection of a CPU write to the 8-bit shift
register (SPDR)). The SCK is based on the internal processor clock. This clock is also used in the 3-bit
counter and 8-bit shift register. See Figure 8-2.
When data is written to the 8-bit shift register of the master device, it is then shifted out to the SDO pin for
application to the slave device. At the same time, data applied from the slave device via the SDI pin is
shifted into the 8-bit shift register.
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