參數資料
型號: MC68HC05L16CFU
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, QFP-80
文件頁數: 110/146頁
文件大?。?/td> 852K
代理商: MC68HC05L16CFU
Oscillators/Clock Distributions
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
66
Freescale Semiconductor
7.5.6 Timebase Control Register 2
Read
Anytime (Bits 3 and 0 are write-only bits and always read as logic 0.)
Write
Anytime (Bit 7 is a read-only bit and write has no effect; bit 1 is 1-time write bit.)
TBIF — Timebase Interrupt Flag
The TBIF bit is set every timeout interval of the timebase counter. This read-only bit is cleared by
writing a logic 1 to the RTBIF bit. Reset clears the TBIF bit. The timebase interrupt period between
reset and the first TBIF depends on the time elapsed during reset, since the timebase divider is not
initialized on reset.
TBIE — Timebase Interrupt Enable
The TBIE bit enables the timebase interrupt capability. If TBIF = 1 and TBIE = 1, the timebase interrupt
is generated.
0 = Timebase interrupt disabled
1 = Timebase interrupt requested when TBIF = 1
TBR1 and TBR0 — Timebase Interrupt Rate Select
The TBR1 and TBR0 bits select one of four rates for the timebase interrupt period (see Table 7-3). The
TBS rate is also related to the COP timeout reset period. These bits are set to logic 1 on reset.
RTBIF — Reset TBS Interrupt Flag
The RTBIF bit is a write-only bit and is always read as logic 0. Writing logic 1 to this bit clears the TBIF
bit and writing logic 0 to this bit has no effect.
Bit 2 — Reserved
This bit is not used and is always read as logic 0.
Address:
$0011
Bit 7
654321
Bit 0
Read:
TBIF
TBIE
TBR1
TBR0
0
00
Write:
RTBIF
COPE
COPC
Reset:
00110000
= Unimplemented
Figure 7-6. Timebase Control Register 2 (TBCR2)
Table 7-5. Timebase Interrupt Frequency
TBCR2
Divide Ratio
Frequency (Hz)
TBR1
TBR0
OSC = 4.0 M
OSC = 4.1943 M
XOSC = 32.768 k
00
TBCLK
÷ 128
244
256
01
TBCLK
÷ 4096
7.63
8.00
10
TBCLK
÷ 8192
3.81
4.00
11
TBCLK
÷ 16,384
1.91
2.00
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