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參數(shù)資料
| 型號： | MC68HC05L16CFU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 118/146頁 |
| 文件大?。?/td> | 852K |
| 代理商： | MC68HC05L16CFU |
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Registers
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
73
8.6 Registers
Three registers in the SSPI provide control, status, and data storage functions. They are:
Serial peripheral control register, SPCR location $000A
Serial peripheral status register, SPSR location $000B
Serial peripheral data register, SPDR location $000C
8.6.1 Serial Peripheral Control Register
SPIE — SSPI Interrupt Enable
If the serial peripheral interrupt enable (SPIE) bit is set, an interrupt is generated when SPIF in the
SPSR is set and I bit (interrupt mask bit) in the condition code register (CCR) is clear.
During stop mode, an SSPI request is accepted only in slave mode. Interrupt in master mode will be
pending until stop mode is exited. STOP instruction does not change SPIF and SPIE.
0 = Disable SSPI interrupt
1 = Enable SSPI interrupt
SPE — SSPI Enable
When the SSPI enable (SPE) bit is set, the SSPI system is enabled and connected to the port C pins.
Clearing the SPE bit initializes all control logic in the SSPI modules and disconnects the SSPI from
port C pins.
This bit is cleared on reset.
0 = Disable SSPI
1 = Enable SSPI
DORD — Data Transmission ORDer
When this bit is set, the data in the 8-bit shift register (SPDR) is shifted in/out from the LSB. When this
bit is cleared, the data in the SPDR is shifted in/out from the MSB.
This bit is cleared on reset.
0 = MSB first
1 = LSB first
MSTR — MaSTeR Mode Select
The MSTR bit determines whether the device is in master mode or slave mode.
In master mode (MSTR = 1), the SCK pin is configured as an output and the serial clock is generated
by the internal clock generator when the CPU writes to the SPDR.
In slave mode (MSTR = 0), the SCK pin is configured as an input and the serial clock is applied
externally. This bit is cleared on reset.
0 = Slave mode
1 = Master mode
Address:
$000A
Bit 7
654321
Bit 0
Read:
SPIE
SPE
DORD
MSTR
0
SPR
Write:
Reset:
00000000
Figure 8-4. Serial Peripheral Control Register (SPCR)
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