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參數(shù)資料
| 型號： | MC68HC05BD5P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 73/112頁 |
| 文件大?。?/td> | 676K |
| 代理商： | MC68HC05BD5P |
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MC68HC05BD3
MOTOROLA
8-3
SYNC SIGNAL PROCESSOR
8
8.1.1.2
Separate Horizontal Or Composite Sync Input
Since the input at HSYNC can be either a pure horizontal sync signal or a composite sync signal,
different methodologies are used in polarity correction.
Unlike the polarity correction for VSYNC, both the high pulse and low pulse of the sync signal at
HSYNC are examined. If the pulse, either active high or low, is longer than a certain period (8
s
or 16 tCYC), it will be regarded as a long pulse. If there are 8 consecutive low long pulses, the input
sync signal will be conrmed as a positive polarity sync signal, and will be inverted. If there are 8
consecutive high long pulses, it will be conrmed as a negative polarity sync signal.
The operation of this module is also continuous, and the error margin is equal to the period of the
pre-set number (default is 8) of horizontal sync pulses. At power-up or system reset, negative
polarity at input is assumed.
8.1.2
Sync Detection
The sync detector determines whether the incoming sync signal is active. Both sync high and low
pulse widths must be within the specic values to be regarded as active. HDET and VDET ags
will be set if the HSYNC and VSYNC signals are active, respectively.
Figure 8-2 Sync Signal Polarity Correction
Negative polarity pure horizontal sync signal
Positive polarity pure horizontal sync signal
Negative polarity composite sync signal
Positive polarity composite sync signal
TPG
61
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