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參數(shù)資料
| 型號： | MC68HC05BD5P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 49/112頁 |
| 文件大小： | 676K |
| 代理商： | MC68HC05BD5P |
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MC68HC05BD3
MOTOROLA
5-1
MULTI-FUNCTION TIMER
5
MULTI-FUNCTION TIMER
The MFT provides miscellaneous functions to the MC68HC05BD3 MCU. It includes a timer
overow function, real-time interrupt, and COP watchdog. The external interrupt (IRQ) triggering
option is also set by this module’s MFT Control and Status Register.
The clock base for this module is derived from the bus clock divided by four. For a 2MHz E (CPU)
clock, the clock base is 0.5MHz. This clock base is then divided by an 8-stage ripple counter to
generate the timer overow. Timer overow rate is thus E/1024. The output of this 8-stage ripple
counter then drives a 4-stage divider to generate real time interrupt. Hence, the clock base for real
time interrupt is E/16384. Real time interrupt rate is selected by RT0 and RT1 bits of MFT Control
and Status register. The interrupt rates are E/16384, (E/16384)/2, (E/16384)/4, and (E/16384)/8.
The selected real time interrupt rate is then divided by 8 to generate COP reset.
5.1
MFT Counter Register
The MFT counter register (MFTCR) can be read at location $0009. It is cleared by reset.
5.2
MFT Control and Status Register
Register bit denitions:
TOF - Timer Overow
1 (set)
–
8-bit ripple timer overow has occurred.
0 (clear) –
No 8-bit ripple timer overow has occurred.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
MFT Control and Status Register
$1C
TOF
RTIF
TOFIE
RTIE
IRQN
RT1
RT0
0000 0011
TPG
39
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