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參數(shù)資料
| 型號(hào)： | MC68HC05BD5P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 62/112頁 |
| 文件大?。?/td> | 676K |
| 代理商： | MC68HC05BD5P |
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MC68HC05BD3
MOTOROLA
7-7
M-BUS SERIAL INTERFACE
7
7.3.3
M-Bus Control Register (MCR)
Register bit denitions:
MEN - M-Bus Enable
1 (set)
–
M-Bus interface system enabled.
0 (clear) –
M-Bus interface system disabled.
MIEN - M-Bus Interrupt Enable
1 (set)
–
M-Bus interrupt enabled.
0 (clear) –
M-Bus interrupt disabled.
This bit enables the MIF (in MSR) for M-Bus interrupts.
MSTA - Master/Slave Select
1 (set)
–
M-Bus is set for master mode operation.
0 (clear) –
M-Bus is set for slave mode operation.
Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated
on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal
is generated and the operation mode changes from master to slave. In master mode, a bit clear
immediately followed by a bit set of this bit generates a repeated START signal without generating
a STOP signal.
MTX - Transmit/Receive Mode Select
1 (set)
–
M-Bus is set for transmit mode.
0 (clear) –
M-Bus is set for receive mode.
TXAK - Acknowledge Enable
1 (set)
–
Do not send acknowledge signal.
0 (clear) –
Send acknowledge signal at 9th clock bit.
If cleared, an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one
byte of data. If set, no acknowledge signal response. This is an active low control bit.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0019
MEN
MIEN
MSTA
MTX
TXAK
0000 0000
TPG
51
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