參數(shù)資料
型號: MC56F8357MPY60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: PLASTIC, LQFP-160
文件頁數(shù): 98/176頁
文件大小: 2230K
代理商: MC56F8357MPY60
56F8357 Technical Data, Rev. 9.0
28
Freescale Semiconductor
Preliminary
TDO
140
Output
Tri-stated
Test Data Output — This tri-stateable output pin provides a
serial output data stream from the JTAG/EOnCE port. It is
driven in the shift-IR and shift-DR controller states, and
changes on the falling edge of TCK.
TRST
136
Schmitt
Input
Input, pulled
high
internally
Test Reset — As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted whenever RESET is
asserted. The only exception occurs in a debugging
environment when a hardware device reset is required and the
JTAG/EOnCE module must not be reset. In this case, assert
RESET, but do not assert TRST.
To deactivate the internal pull-up resistor, set the JTAG bit in
the SIM_PUDR register.
PHASEA0
(TA0)
(GPIOC4)
155
Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Input
Phase A — Quadrature Decoder 0, PHASEA input
TA0 — Timer A, Channel 0
Port C GPIO — This GPIO pin can be individually programmed
as an input or output pin.
After reset, the default state is PHASEA0.
To deactivate the internal pull-up resistor, clear bit 4 of the
GPIOC_PUR register.
PHASEB0
(TA1)
(GPIOC5)
156
Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Input
Phase B — Quadrature Decoder 0, PHASEB input
TA1 — Timer A ,Channel
Port C GPIO — This GPIO pin can be individually programmed
as an input or output pin.
After reset, the default state is PHASEB0.
To deactivate the internal pull-up resistor, clear bit 5 of the
GPIOC_PUR register.
Table 2-2 Signal and Package Information for the 160-Pin LQFP
Signal Name
Pin
No.
Type
State
During
Reset
Signal Description
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