參數(shù)資料
型號: MC56F8357MPY60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: PLASTIC, LQFP-160
文件頁數(shù): 49/176頁
文件大?。?/td> 2230K
代理商: MC56F8357MPY60
56F8357 Technical Data, Rev. 9.0
142
Freescale Semiconductor
Preliminary
Table 10-16 External Memory Interface Timing
Characteristic
Symbol
Wait States
Configuration
DM
Wait States
Controls
Unit
Address Valid to WR Asserted
tAWR
WWS=0
-1.477
0.50
WWSS
ns
WWS>0
-1.564
0.75 + DCAOE
WR Width Asserted to WR
Deasserted
tWR
WWS=0
-0.186
0.25 + DCAOE
WWS
ns
WWS>0
-0.256
0
Data Out Valid to WR Asserted
tDWR
WWS=0
-9.568
0.25 + DCAEO
WWSS
ns
WWS=0
-1.721
0.00
WWS>0
-9.227
0.50
WWS>0
-1.808
0.25 + DCAOE
Valid Data Out Hold Time after WR
Deasserted
tDOH
-2.287
0.25 + DCAEO
WWSH
ns
Valid Data Out Set-Up Time to
WR Deasserted
tDOS
-1.622
0.25 + DCAOE
WWS,WWSS
ns
-9.041
0.50
Valid Address after WR
Deasserted
tWAC
-3.918
0.25 + DCAEO
WWSH
ns
RD Deasserted to Address Invalid
tRDA
-2.229
0.00
RWSH
ns
Address Valid to RD Deasserted
tARDD
-1.887
1.00
RWSS,RWS
ns
Valid Input Data Hold after RD
Deasserted
tDRD
0.00
N/A1
1. N/A, since device captures data before it deasserts RD
ns
RD Assertion Width
tRD
0.212
1.00
RWS
ns
Address Valid to Input Data Valid
tAD
-14.427
1.00
RWSS,RWS
ns
-19.751
1.25 + DCAOE
Address Valid to RD Asserted
tARDA
-2.121
0.00
RWSS
ns
RD Asserted to Input Data Valid
tRDD
-12.306
1.00
RWSS,RWS
ns
-17.630
1.25 + DCAOE
WR Deasserted to RD Asserted
tWRRD
-1.923
0.25 + DCAEO
WWSH,RWSS
ns
RD Deasserted to RD Asserted
tRDRD
-0.2342
2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads.
0.00
RWSS,RWSH
MDAR3, 4
3. Substitute BMDAR for MDAR if there is no chip select
4. MDAR is active in this calculation only when the chip select changes.
ns
WR Deasserted to WR Asserted
tWRWR
WWS=0
-1.279
0.75 + DCAEO
WWSS, WWSH
ns
WWS>0
-0.938
1.00
RD Deasserted to WR Asserted
tRDWR
WWS=0
-0.046
0.50
RWSH, WWSS,
MDAR3
ns
WWS>0
0.052
0.75 + DCAOE
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