參數(shù)資料
型號: MC56F8357MPY60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: PLASTIC, LQFP-160
文件頁數(shù): 12/176頁
文件大小: 2230K
代理商: MC56F8357MPY60
Register Descriptions
56F8357 Technical Data, Rev. 9.0
Freescale Semiconductor
109
Preliminary
In addition, this pin can be used as a general purpose input pin after reset.
0 = External address bits [19:16] are initially programmed as GPIO
1 = When booted with EXTBOOT = 1, A[19:16] are initially programmed as address. If EXTBOOT is 0,
they are initialized as GPIO.
6.5.1.3
OnCE Enable (OnCE EBL)—Bit 5
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
6.5.1.4
Software Reset (SW RST)—Bit 4
This bit is always read as 0. Writing a 1 to this bit will cause the part to reset.
6.5.1.5
Stop Disable (STOP_DISABLE)—Bits 3–2
00 - Stop mode will be entered when the 56800E core executes a STOP instruction
01 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be
reprogrammed in the future
10 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then only be
changed by resetting the device
11 - Same operation as 10
6.5.1.6
Wait Disable (WAIT_DISABLE)—Bits 1–0
00 - Wait mode will be entered when the 56800E core executes a WAIT instruction
01 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be
reprogrammed in the future
10 - The HawkV2 WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then only
be changed by resetting the device
11 - Same operation as 10
6.5.2
SIM Reset Status Register (SIM_RSTSTS)
Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A
reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this
register.
Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)
Base + $1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
O
0
SWR
COPR
EXTR
POR
0
Write
RESET
0
00
0
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