參數(shù)資料
型號: MC56F8357MPY60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: PLASTIC, LQFP-160
文件頁數(shù): 95/176頁
文件大?。?/td> 2230K
代理商: MC56F8357MPY60
Signal Pins
56F8357 Technical Data, Rev. 9.0
Freescale Semiconductor
25
Preliminary
WR
51
Output
Tri-stated
Write Enable — WR is asserted during external memory write
cycles. When WR is asserted low, pins D0 - D15 become
outputs and the device puts data on the bus. When WR is
deasserted high, the external data is latched inside the external
device. When WR is asserted, it qualifies the A0 - A23, PS, DS,
and CSn pins. WR can be connected directly to the WE pin of a
static RAM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), WR is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in
the SIM_PUDR register.
PS
(CS0)
(GPIOD8)
53
Output
Input/
Output
Tri-stated
Input
Program Memory Select — This signal is actually CS0 in the
EMI, which is programmed at reset for compatibility with the
56F80x PS signal. PS is asserted low for external program
memory access.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS0 is tri-stated when the external bus is inactive.
CS0 resets to provide the PS function as defined on the
56F80x devices.
Port D GPIO — This GPIO pin can be individually programmed
as an input or output pin.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
Table 2-2 Signal and Package Information for the 160-Pin LQFP
Signal Name
Pin
No.
Type
State
During
Reset
Signal Description
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