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參數(shù)資料
| 型號： | MC56F8323 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-bit Hybrid Controllers |
| 中文描述： | 16位混合控制器 |
| 文件頁數(shù)： | 34/140頁 |
| 文件大?。?/td> | 1981K |
| 代理商： | MC56F8323 |
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Equivalent Circuit for ADC Inputs
56F8323 Technical Data, Rev. 11.0
Freescale Semiconductor
129
Preliminary
10.16 Equivalent Circuit for ADC Inputs
Figure 10-22 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed
at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and
hold circuit moves to (VREFH-VREFLO)/2, while the other charges to the analog input voltage. When the
switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (VREFH-VREFLO)/2. The switches switch
on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there
are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into
the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, VREF and the ADC clock frequency.
1.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf
2.
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf
3.
Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms
4.
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1pf
Figure 10-22 Equivalent Circuit for A/D Loading
10.17 Power Consumption
See Part 10 for a list of IDD requirements for the 56F8323. This section provides additional detail which
can be used to optimize power consumption for a given application.
Power consumption is given by the following equation:
A, the internal [static component], is comprised of the DC bias currents for the oscillator, current, PLL,
and voltage references. These sources operate independently of processor state or operating frequency.
B, the internal [state-dependent component], reflects the supply current required by certain on-chip
resources only when those resources are in use. These include RAM, Flash memory and the ADCs.
Total power =
A: internal [static component]
+B: internal [state-dependent component]
+C: internal [dynamic component]
+D: external [dynamic component]
+E: external [static]
1
2
3
Analog Input
4
S1
S2
S3
C1
C2
S/H
C1 = C2 = 1pF
(VREFH - VREFLO)/2
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC56F8323EVM | 功能描述:開發(fā)板和工具包 - 其他處理器 MC56F832X Dev Kit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MC56F8323EVM | 制造商:Freescale Semiconductor 功能描述:Tools Development kit Kit Con |
| MC56F8323EVME | 功能描述:開發(fā)板和工具包 - 其他處理器 MC56F8323 EVAL BRD RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MC56F8323EVME | 制造商:Freescale Semiconductor 功能描述:Evaluation Kit for MC56F832x and MC56F81 |
| MC56F8323MFB60 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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