參數(shù)資料
型號: MC56F8322VFAE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 120 MHz, OTHER DSP, PQFP48
封裝: ROHS COMPLIANT, LQFP-48
文件頁數(shù): 57/136頁
文件大?。?/td> 719K
代理商: MC56F8322VFAE
Signal Pins
56F8322 Technical Data, Rev. 16
Freescale Semiconductor
27
Preliminary
TC1
(RXD0)
(GPIOC5)
48
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
TC1 — Timer C, Channel 1
Receive Data — SCI0 receive data input
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is TC1.
IRQA
(VPP)
11
Schmitt
Input
Input,
pull-up
enabled
External Interrupt Request A — The IRQA input is an asynchronous
external interrupt request during Stop and Wait mode operation.
During other operating modes, it is a synchronized external interrupt
request which indicates an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered.
VPP — This pin is used for Flash debugging purposes.
RESET
2Schmitt
Input
Input,
pull-up
enabled
Reset — This input is a direct hardware reset on the processor. When
RESET is asserted low, the hybrid controller is initialized and placed
in the reset state. A Schmitt trigger input is used for noise immunity.
The internal reset signal will be deasserted synchronous with the
internal clocks after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware DSP reset is required and it is
necessary not to reset the JTAG/EOnCE module. In this case, assert
RESET, but do not assert TRST.
Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal Name
Pin No.
Type
State During
Reset
Signal Description
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