參數(shù)資料
型號: MC56F8322VFAE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 120 MHz, OTHER DSP, PQFP48
封裝: ROHS COMPLIANT, LQFP-48
文件頁數(shù): 51/136頁
文件大?。?/td> 719K
代理商: MC56F8322VFAE
Signal Pins
56F8322 Technical Data, Rev. 16
Freescale Semiconductor
21
Preliminary
PHASEA0
(TA0)
(GPIOB7)
(oscillator_
clock)
38
Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
Phase A — Quadrature Decoder 0, PHASEA input
TA0 — Timer A, Channel 0
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Clock Output - can be used to monitor the internal oscillator clock
signal (see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8322, the default state after reset is PHASEA0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
PHASEB0
(TA1)
(GPIOB6)
(SYS_CLK2)
37
Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
Phase B — Quadrature Decoder 0, PHASEB input
TA1 — Timer A ,Channel 1
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Clock Output - can be used to monitor the internal SYS_CLK2 signal
(see Section 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8322, the default state after reset is PHASEB0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal Name
Pin No.
Type
State During
Reset
Signal Description
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