參數(shù)資料
型號(hào)： MC56F8322VFAE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 120 MHz, OTHER DSP, PQFP48
封裝： ROHS COMPLIANT, LQFP-48
文件頁數(shù)： 27/136頁
文件大?。?/td> 719K
代理商： MC56F8322VFAE
56F8322 Techncial Data, Rev. 16
122
Freescale Semiconductor
Preliminary
ADC channel power-up time
tADPU
56
16
tAIC cycles
3
ADC reference circuit power-up time4
tVREF
——25
ms
Conversion time
tADC
—6
—
tAIC cycles
3
Sample time
tADS
—1
—
tAIC cycles
3
Input capacitance
CADI
—5
—
pF
Input injection current5, per pin
IADI
——
3
mA
Input injection current, total
IADIT
——20
mA
VREFH current
IVREFH
—1.2
3
mA
ADC A current
IADCA
—25
—
mA
ADC B current
IADCB
—25
—
mA
Quiescent current
IADCQ
—010
μA
Uncalibrated Gain Error (ideal)
EGAIN
—
+/- .004
+/- .01
—
Uncalibrated Offset Voltage
VOFFSET
—
+/- 26
+/- 32
mV
Calibrated Absolute Error6
AECAL
—
LSBs
Calibration Factor 17
CF1
—
0.008597
—
Calibration Factor 27
CF2
—
-2.8
—
Crosstalk between channels
——
-60
—
dB
Common Mode Voltage
Vcommon
—(VREFH - VREFLO) / 2
—
V
Signal-to-noise ratio
SNR
—
64.6
—
db
Signal-to-noise plus distortion ratio
SINAD
—
59.1
—
db
Total Harmonic Distortion
THD
—
60.6
—
db
Spurious Free Dynamic Range
SFDR
—
61.1
—
db
Effective Number Of Bits8
ENOB
—
9.6
—
Bits
1. INL measured from Vin = .1VREFH to Vin = .9VREFH
10% to 90% Input Signal Range
2. LSB = Least Significant Bit
3. ADC clock cycles
4. Assumes each voltage reference pin is bypassed with 0.1
μF ceramic capacitors to ground
5. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of
the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible.
6. Absolute error includes the effects of both gain error and offset error.
7. Please see the 56F8300 Peripheral User’s Manual for additional information on ADC calibration.
8. ENOB = (SINAD - 1.76)/6.02
Table 10-24 ADC Parameters (Continued)
Characteristic
Symbol
Min
Typ
Max
Unit
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參數(shù)描述
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