參數(shù)資料
型號(hào)： MC56F8147VVFE
廠商： Freescale Semiconductor
文件頁數(shù)： 86/172頁
文件大?。?/td> 0K
描述： IC DGTL SIGNAL CTLR 160-MAPBGA
標(biāo)準(zhǔn)包裝： 126
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 40MHz
連通性： EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 76
程序存儲(chǔ)器容量： 128KB（64K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 160-BGA
包裝： 托盤
56F8347 Technical Data, Rev.11
20
Freescale Semiconductor
Preliminary
XTAL
93
K12
Input/
Output
Chip-
driven
Crystal Oscillator Output — This output connects the
internal crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input
and EXTAL connected to GND.
The input clock can be selected to provide the clock directly
to the core. This input clock can also be selected as the input
clock for the on-chip PLL.
CLKO
3
D3
Output
In reset,
output is
disabled
Clock Output — This pin outputs a buffered clock signal.
Using the SIM CLKO Select Register (SIM_CLKOSR), this
pin can be programmed as any of the following: disabled,
CLK_MSTR (system clock), IPBus clock, oscillator output,
prescaler clock and postscaler clock. Other signals are also
available for test purposes.
See Part 6.5.7 for details.
A0
(GPIOA8)
154
C3
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Address Bus — A0 - A5 specify six of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A0 - A5 and EMI control signals are
tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
Port A GPIO — These six GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOA_PUR register.
Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.
A1
(GPIOA9)
10
E3
A2
(GPIOA10)
11
E4
A3
(GPIOA11)
12
F2
A4
(GPIOA12)
13
F1
A5
(GPIOA13)
14
F3
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal Name
Pin
No.
Ball
No.
Type
State
During
Reset
Signal Description
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