參數(shù)資料
型號： MC56F8147VVFE
廠商： Freescale Semiconductor
文件頁數(shù)： 83/172頁
文件大?。?/td> 0K
描述： IC DGTL SIGNAL CTLR 160-MAPBGA
標準包裝： 126
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 40MHz
連通性： EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 76
程序存儲器容量： 128KB（64K x 16）
程序存儲器類型： 閃存
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 160-BGA
包裝： 托盤
56F8347 Technical Data, Rev.11
18
Freescale Semiconductor
Preliminary
2.2 Signal Pins
After reset, all pins are by default the primary function. Any alternate functionality must be programmed.
Note: Signals in italics are NOT available in the 56F8147 device.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin
shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the
pin, it will become an input if no other registers are changed.
Note: LQFP Pin numbers and MBGA Ball numbers do not always correlate in Table 2-2. Please contact
factory for exact correlation.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
Signal Name
Pin
No.
Ball
No.
Type
During
Reset
Signal Description
VDD_IO
1
F4
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O
interface and also the Processor core throught the on-chip
voltage regulator, if it is enabled.
VDD_IO
16
K5
VDD_IO
31
E5
VDD_IO
42
K7
VDD_IO
77
E9
VDD_IO
96
K10
VDD_IO
134
F11
VDDA_ADC
114
C14
Supply
ADC Power — This pin supplies 3.3V power to the ADC
modules. It must be connected to a clean analog power
supply.
VDDA_OSC_
PLL
92
K13
Supply
Oscillator and PLL Power — This pin supplies 3.3V power
to the OSC and to the internal regulator that in turn supplies
the Phase Locked Loop. It must be connected to a clean
analog power supply.
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