參數(shù)資料
型號: MC56F8147VVFE
廠商: Freescale Semiconductor
文件頁數(shù): 43/172頁
文件大?。?/td> 0K
描述: IC DGTL SIGNAL CTLR 160-MAPBGA
標準包裝: 126
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 76
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 160-BGA
包裝: 托盤
External Clock Operation Timing
56F8347 Technical Data, Rev.11
Freescale Semiconductor
137
Preliminary
10.5 External Clock Operation Timing
Figure 10-3 External Clock Timing
10.6 Phase Locked Loop Timing
Table 10-13 External Clock Operation Timing Requirements1
1. Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)2
2. See Figure 10-3 for details on using the recommended connection of an external clock driver.
fosc
0—
120
MHz
Clock Pulse Width3
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
tPW
3.0
ns
External clock input rise time4
4. External clock input rise time is measured from 10% to 90%.
trise
10
ns
External clock input fall time5
5. External clock input fall time is measured from 90% to 10%.
tfall
10
ns
Table 10-14 PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 8MHz input crystal.
fosc
48
8.4
MHz
PLL output frequency2 (fOUT)
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (fOUT/2), please refer to the OCCS chapter in
the 56F8300 Peripheral User Manual.
fop
160
260
MHz
PLL stabilization time3 -40
° to +125°C
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
tplls
—1
10
ms
External
Clock
VIH
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
90%
50%
10%
90%
50%
10%
tPW
tfall
trise
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