參數(shù)資料
型號(hào)： MC56603AGC60
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-BIT, 60 MHz, OTHER DSP, PBGA144
封裝： PLASTIC, BGA-144
文件頁(yè)數(shù)： 4/97頁(yè)
文件大?。?/td> 1080K
代理商： MC56603AGC60
1-6
DSP56603A Technical Data Sheet
MOTOROLA
DSP56603A
Interrupt And Mode Control
INTERRUPT AND MODE CONTROL
Table 1-5
Interrupt and Mode Control Signals
Signal
Name
Signal
Type
State
During
Reset
Signal Description
RESET
Input
Reset
RESET is an active low, Schmitt-trigger input. Deassertion of the
RESET signal is internally synchronized to the clock out (CLKOUT).
When asserted, the chip is placed in the Reset state and the internal
phase generator is reset. The Schmitt-trigger input allows a slowly rising
input, such as a capacitor charging, to reliably reset the chip. If the
RESET signal is deasserted synchronous to CLKOUT, exact start-up
timing is guaranteed, allowing multiple processors to start up
synchronously and operate together. When the RESET signal is
deasserted, the initial chip operating mode is latched from the MODA,
MODB, MODC, and MODD inputs. In addition, the value on the PINIT/
NMI pin is latched to the PEN bit in the PCTL1 register.
MODA
IRQA
Input
Mode Select A
During hardware reset, MODA, MODB, MODC, and
MODD select one of sixteen initial chip operating modes latched into the
Operating Mode Register (OMR) when the RESET signal is deasserted.
External Interrupt Request A
Following RESET deassertion, MODA
becomes IRQA, a level-sensitive or negative-edge-triggered, maskable
interrupt request input during normal instruction processing. If IRQA is
asserted synchronous to CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and asserting IRQA to exit
the Wait state. If the processor is in the Stop standby state and IRQA is
asserted, the processor exits the Stop state.
This is an active low Schmitt-trigger input, internally synchronized to
CLKOUT.
MODB
IRQB
Input
Mode Select B
During hardware reset, MODA, MODB, MODC, and
MODD select one of sixteen initial chip operating modes latched into the
Operating Mode Register (OMR) when the RESET signal is deasserted.
External Interrupt Request B
Following RESET deassertion, MODB
becomes IRQB, a level-sensitive or negative-edge-triggered, maskable
interrupt request input during normal instruction processing. If IRQB is
asserted synchronous to CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and asserting IRQB to exit
the Wait state. If the processor is in the Stop standby state and IRQB is
asserted, the processor exits the Stop state.
This is an active low Schmitt-trigger input, internally synchronized to
CLKOUT.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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