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參數資料
| 型號： | MC56603AGC60 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | 24-BIT, 60 MHz, OTHER DSP, PBGA144 |
| 封裝： | PLASTIC, BGA-144 |
| 文件頁數： | 30/97頁 |
| 文件大小： | 1080K |
| 代理商： | MC56603AGC60 |
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2-8
DSP56603A Technical Data Sheet
MOTOROLA
DSP56603A
AC Electrical Characteristics
AC Electrical CharacteristicsReset, Stop, Mode Select, and Interrupt
Timing
(VCC = 3.0 V ±0.3 V; TA = 40 to 85C, CL = 70 pF + 2 TTL Loads)
WS = Number of Wait States (measured in clock cycles, number of TC)
Table 2-8
Reset Timing
Num
Characteristics
Expression
60 MHz
Unit
Min Max
8
Delay from RESET assertion to all pins at reset value1
20.0 + TC
333.34
ns
9
Required RESET duration 1, 2, 3
Power on, external clock generator, PLL disabled
Power on, external clock generator, PLL enabled
Power on, internal oscillator
During Stop, XTAL disabled
During Stop, XTAL enabled
During normal operation
50
ETC
1000
ETC
75000
ETC
75000
ETC
2.5
TC
2.5
TC
833.3
16.72
1.25
41.7
ns
s
ms
ns
10
Delay from asynchronous RESET deassertion to first
external address output (internal reset deassertion)4
Minimum
Maximum
3.25
TC + 2.2
20.25TC + 12.1
56.4
349.6
ns
11
Synchronous reset setup time from RESET deassertion to
first CLKOUT transition
TC
9.0
16.7
ns
12
Synchronous reset deassertion, delay time from the first
CLKOUT transition to the first external address output
Minimum
Maximum
3.25
TC + 1.1
20.25TC + 5.5
55.3
343.0
ns
Notes:
1.
These timings are periodically sampled and not 100% tested.
2.
For an external clock generator, RESET duration is measured during the time in which RESET is
asserted, VCC is valid, and the EXTAL input is active and valid. For internal oscillator, RESET duration
is measured during the time in which RESET is asserted and VCC is valid. The specified timing reflects
the crystal oscillator stabilization time after power-up. This number is affected both by the
specifications of the crystal and other components connected to the oscillator and reflects worst case
conditions.
3.
When VCC is powered up and the Required RESET Duration conditions as specified above are not yet
met, the device circuitry is in an uninitialized state that may result in significant power consumption.
Designs should minimize this state to the shortest possible duration.
4.
This specification is valid if the PLL does not lose lock.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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