參數(shù)資料
型號(hào)： MC56603AGC60
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-BIT, 60 MHz, OTHER DSP, PBGA144
封裝： PLASTIC, BGA-144
文件頁(yè)數(shù)： 16/97頁(yè)
文件大?。?/td> 1080K
代理商： MC56603AGC60
DSP56603A
Synchronous Serial Interface 1 (SSI1)
MOTOROLA
DSP56603A Technical Data Sheet
1-17
SYNCHRONOUS SERIAL INTERFACE 1 (SSI1)
Table 1-9
Synchronous Serial Interface 1 (SSI1)
Signal
Name
Signal Type
State
During
Reset
Signal Description
SC10
PD0
Input or
Output
Input or
Output
Tri-stated Serial Control Signal 0The function of SC10 is determined
by the selection of either Synchronous or Asynchronous
mode. For Asynchronous mode, this signal is used for the
receive clock I/O (Schmitt-trigger input). For Synchronous
mode, this signal is used for or for Serial I/O Flag 0.
Port D 0
When configured as PD0, signal direction is
controlled through the SSI1 Port Direction Control Register
(PRRD). The signal can be configured as SSI signal SC10
through the SSI1 Port Control Register (PCRD).
This pin is electrically disconnected internally during the
Stop processing state.
SC11
PD1
Input or
Output
Input or
Output
Tri-stated Serial Control Signal 1The function of SC11 is determined
by the selection of either Synchronous or Asynchronous
mode. For Asynchronous mode, this signal is used for the
receive clock I/O (Schmitt-trigger input). For Synchronous
mode, this signal is used for Serial I/O Flag 1.
Port D 1
When configured as PD1, signal direction is
controlled through the PRRD. The signal can be configured
as an SSI signal SC11 through the PCRD.
This pin is electrically disconnected internally during the
Stop processing state.
SC12
PD2
Input or
Output
Input or
Output
Tri-stated Serial Control Signal 2SC12 is used for frame sync I/O.
SC12 is the frame sync for both the transmitter and receiver
in Synchronous mode, and for the transmitter only in
Asynchronous mode. When configured as an output, this
signal is the internally generated frame sync signal. When
configured as an input, this signal receives an external frame
sync signal for the transmitter (and the receiver in
synchronous operation).
Port D 2
When configured as PD2, signal direction is
controlled through the PRRD. The signal can be configured
as an SSI signal SC12 through the PCRD.
This pin is electrically disconnected internally during the
Stop processing state.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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