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參數(shù)資料
| 型號： | MC145152DW2R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PAR-IN PLL FREQ SYNTH 28-SOIC |
| 標準包裝： | 1,000 |
| 類型： | PLL 時鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 25MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 9 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MC145152DW2TR |
MC145151-2 and MC145152-2 Electrical Characteristics
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
17
Figure 11. Phase Detector/Lock Detector Output Waveforms
Table 6. Frequency Characteristics
(Voltages References to VSS, CL = 50 pF, Input tr = tf =10 ns unless otherwise indicated)
Symbol
Parameter
Test Condition
VDD
V
- 40
°C
25
°C
85
°C
Unit
Min
Max
Min
Max
Min
Max
fi
Input Frequency
(fin, OSCin)
R
≥ 8, A ≥ 0, N ≥ 8
Vin = 500 mV p-p ac coupled
sine wave
3
5
9
-
6
15
-
6
15
-
6
15
MHz
R
≥ 8, A ≥ 0, N ≥ 8
Vin = 1 V p-p ac coupled
sine wave
3
5
9
-
12
22
25
-
12
20
22
-
7
20
22
MHz
R
≥ 8, A ≥ 0, N ≥ 8
Vin = VDD to VSS dc coupled
square wave
3
5
9
-
13
25
-
12
22
25
-
8
22
25
MHz
Note: Usually, the PLL's propagation delay from fin to MC plus the setup time of the prescaler determines the upper frequency
limit of the system. The upper frequency limit is found with the following formula: f = P/(tP + tset) where f is the upper frequency
in Hz, P is the lower of the dual modulus prescaler ratios, tP is the fin to MC propagation delay in seconds, and tset is the prescaler
setup time in seconds. For example, with a 5 V supply, the fin to MC delay is 70 ns. If the MC12028A prescaler is used, the setup
time is 16 ns. Thus, if the 64/65 ratio is utilized, the upper frequency limit is f = P/(tP + tset) = 64/(70 + 16) = 744 MHz.
VH=High Voltage Level.
VL=Low Voltage Level.
* At this point, when both fR and fV are in phase, the output is forced to near mid-supply.
NOTE: The PDout generates error pulses during out-of-lock conditions. When locked in phase and frequency the output is high
and the voltage at this pin is determined by the low-pass filter capacitor.
fR
REFERENCE
OSC
÷ R
fV
FEEDBACK
(fin ÷ N)
PDout
φ
R
φ
V
LD
*
VH
VL
VH
VL
VH
HIGH IMPEDANCE
VH
VL
VH
VL
VH
VL
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