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參數(shù)資料
| 型號： | MC145152DW2R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PAR-IN PLL FREQ SYNTH 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | PLL 時(shí)鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 25MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 9 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MC145152DW2TR |
Design Considerations
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
21
To verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency
as a function of voltage at OSCout. (Care should be taken to minimize loading.) The frequency should
increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in
frequency or become unstable with an increase in supply voltage. The operating supply voltage must be
reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can
prove very helpful.
4.3
Dual-Modulus Prescaling
4.3.1
Overview
The technique of dual-modulus prescaling is well established as a method of achieving high performance
frequency synthesizer operation at high frequencies. Basically, the approach allows relatively
low-frequency programmable counters to be used as high-frequency programmable counters with speed
capability of several hundred MHz. This is possible without the sacrifice in system resolution and
performance that results if a fixed (single-modulus) divider is used for the prescaler.
In dual-modulus prescaling, the lower speed counters must be uniquely configured. Special control logic
is necessary to select the divide value P or P + 1 in the prescaler for the required amount of time (see
modulus control definition).
4.3.2
Design Guidelines
The system total divide value, Ntotal (NT) will be dictated by the application:
N is the number programmed into the
÷ N counter, A is the number programmed into the ÷ A counter, P
and P + 1 are the two selectable divide ratios available in the dual-modulus prescalers. To have a range of
NT values in sequence, the ÷ A counter is programmed from zero through P - 1 for a particular value N in
the
÷ N counter. N is then incremented to N + 1 and the ÷ A is sequenced from 0 through P - 1 again.
There are minimum and maximum values that can be achieved for NT. These values are a function of P
and the size of the
÷ N and ÷ A counters.
The constraint N
≥ A always applies. If A
max = P - 1, then Nmin ≥ P - 1. Then NTmin = (P - 1) P + A or
(P - 1) P since A is free to assume the value of 0.
NTmax = Nmax P + Amax
To maximize system frequency capability, the dual-modulus prescaler output must go from low to high
after each group of P or P + 1 input cycles. The prescaler should divide by P when its modulus control line
is high and by P + 1 when its MC is low.
NT=
frequency into the prescaler
frequency into the phase detector
= N
P + A
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| MC145155P | 制造商:Motorola Inc 功能描述: |
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| MC145158DW2 | 功能描述:IC SER-IN PLL FREQ SYNTH 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC145158DW2R2 | 制造商: 功能描述: 制造商:undefined 功能描述: |
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