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| 型號(hào)： | MC-424LFG641 |
| 廠商： | NEC Corp. |
| 英文描述： | 64 bits dynamic RAM modules(64 位動(dòng)態(tài)RAM 模塊) |
| 中文描述： | 64位動(dòng)態(tài)RAM模塊（64位動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 8/44頁(yè) |
| 文件大?。?/td> | 368K |
| 代理商： | MC-424LFG641 |
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8
MC-424LFG641
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
[ MC-424LFG641F, 424LFG641FA ]
Parameter
Symbol
Test condition
MIN.
MAX.
Unit
Notes
Operating current
I
CC1
/RAS, /CAS cycling
t
RAC
= 60 ns
1,280
mA
1, 2, 3
t
RC
= t
RC (MIN.)
, I
O
= 0 mA
t
RAC
= 70 ns
1,120
Standby current
I
CC2
/RAS, /CAS
≥
V
IH (MIN.)
, I
O
= 0 mA
32
mA
/RAS, /CAS
≥
V
CC
0.2 V, I
O
= 0 mA
8
/RAS only refresh current
I
CC3
/RAS cycling, /CAS
≥
V
IH (MIN.)
t
RAC
= 60 ns
1,280
mA
1, 2, 3 ,4
t
RC
= t
RC (MIN.)
, I
O
= 0 mA
t
RAC
= 70 ns
1,120
Operating current
I
CC4
/RAS
≤
V
IL (MAX.)
, /CAS cycling
t
RAC
= 60 ns
1,440
mA
1, 2, 5
(Hyper page mode (EDO))
t
HPC
= t
HPC (MIN.)
, I
O
= 0 mA
t
RAC
= 70 ns
1,280
/CAS before /RAS
I
CC5
/RAS cycling
t
RAC
= 60 ns
1,280
mA
1, 2
refresh current
t
RC
= t
RC (MIN.)
, I
O
= 0 mA
t
RAC
= 70 ns
1,120
Input leakage current
I
I (L)
V
I
= 0 to 3.6 V
Address
80
+80
μ
A
All other pins not under test = 0 V
/RAS, /WE, /OE
40
+40
/CAS
10
+10
Output leakage current
I
O (L)
V
O
= 0 to 3.6 V
5
+5
μ
A
Output is disabled (Hi
Z)
High level output voltage
V
OH
I
O
=
2.0 mA
2.4
V
Low level output voltage
V
OL
I
O
= +2.0 mA
0.4
V
Notes 1.
I
CC1
, I
CC3
, I
CC4
and I
CC5
depend on cycle rates (t
RC
and t
HPC
).
2.
Specified values are obtained with outputs unloaded.
3.
I
CC1
and I
CC3
are measured assuming that address can be changed once or less during /RAS
≤
V
IL (MAX.)
and
/CAS
≥
V
IH (MIN.)
.
4.
I
CC3
is measured assuming that all column address inputs are held at either high or low.
5.
I
CC4
is measured assuming that all column address inputs are switched only once during each hyper page
(EDO) cycle.
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