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參數(shù)資料
| 型號(hào)： | MC-424LFG641 |
| 廠商： | NEC Corp. |
| 英文描述： | 64 bits dynamic RAM modules(64 位動(dòng)態(tài)RAM 模塊) |
| 中文描述： | 64位動(dòng)態(tài)RAM模塊（64位動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 16/44頁(yè) |
| 文件大?。?/td> | 368K |
| 代理商： | MC-424LFG641 |
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16
MC-424LFG641
Read Modify Write Cycle
[ MC-424LFG641F, 424LFG641FA ]
Parameter
Symbol
t
RAC
= 60 ns
t
RAC
= 70 ns
Unit
Note
MIN.
MAX.
MIN.
MAX.
Read modify write cycle time
t
RWC
133
157
ns
/RAS to /WE delay time
t
RWD
77
89
ns
1
/CAS to /WE delay time
t
CWD
32
37
ns
1
Column address to /WE delay time
t
AWD
47
54
ns
1
Note
1.
If t
WCS
≥
t
WCS (MIN.)
, the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If t
RWD
≥
t
RWD
(MIN.)
, t
CWD
≥
t
CWD
(MIN.)
, t
AWD
≥
t
AWD
(MIN.)
and t
CPWD
≥
t
CPWD (MIN.)
, the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
[ MC-424LFG641FW ]
Parameter
Symbol
t
RAC
= 50 ns
t
RAC
= 60 ns
Unit
Note
MIN.
MAX.
MIN.
MAX.
Read modify write cycle time
t
RWC
107
133
ns
/RAS to /WE delay time
t
RWD
64
77
ns
1
/CAS to /WE delay time
t
CWD
27
32
ns
1
Column address to /WE delay time
t
AWD
39
47
ns
1
Note
1.
If t
WCS
≥
t
WCS (MIN.)
, the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If t
RWD
≥
t
RWD
(MIN.)
, t
CWD
≥
t
CWD
(MIN.)
, t
AWD
≥
t
AWD
(MIN.)
and t
CPWD
≥
t
CPWD (MIN.)
, the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
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