參數(shù)資料
型號(hào)： MC-424LFG641
廠商： NEC Corp.
英文描述： 64 bits dynamic RAM modules(64 位動(dòng)態(tài)RAM 模塊)
中文描述： 64位動(dòng)態(tài)RAM模塊（64位動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 15/44頁(yè)
文件大?。?/td> 368K
代理商： MC-424LFG641
15
MC-424LFG641
Write Cycle
[ MC-424LFG641F, 424LFG641FA ]
Parameter
Symbol
t
RAC
= 60 ns
t
RAC
= 70 ns
Unit
Notes
MIN.
MAX.
MIN.
MAX.
/WE hold time referenced to /CAS
t
WCH
10
10
ns
1
/WE pulse width
t
WP
10
10
ns
1
/WE lead time referenced to /RAS
t
RWL
15
20
ns
/WE lead time referenced to /CAS
t
CWL
10
12
ns
/WE setup time
t
WCS
0
0
ns
2
/OE hold time
t
OEH
0
0
ns
Data-in setup time
t
DS
0
0
ns
3
Data-in hold time
t
DH
10
15
ns
3
Notes 1.
t
WP
(MIN.)
is applied to late write cycles or read modify write cycles. In early write cycles, t
WCH
(MIN.)
should be met.
2.
If t
WCS
≥
t
WCS
(MIN.)
, the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
3.
t
DS
(MIN.)
and t
DH
(MIN.)
are referenced to the /CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the /WE falling edge.
[ MC-424LFG641FW ]
Parameter
Symbol
t
RAC
= 50 ns
t
RAC
= 60 ns
Unit
Notes
MIN.
MAX.
MIN.
MAX.
/WE hold time referenced to /CAS
t
WCH
7
10
ns
1
/WE pulse width
t
WP
7
10
ns
1
/WE lead time referenced to /RAS
t
RWL
13
15
ns
/WE lead time referenced to /CAS
t
CWL
7
10
ns
/WE setup time
t
WCS
0
0
ns
2
/OE hold time
t
OEH
0
0
ns
Data-in setup time
t
DS
0
0
ns
3
Data-in hold time
t
DH
7
10
ns
3
Notes 1.
t
WP
(MIN.)
is applied to late write cycles or read modify write cycles. In early write cycles, t
WCH
(MIN.)
should be met.
2.
If t
WCS
≥
t
WCS
(MIN.)
, the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
3.
t
DS
(MIN.)
and t
DH
(MIN.)
are referenced to the /CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the /WE falling edge.
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