參數(shù)資料
型號(hào)： MC-10118BF1-ENY-A
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA481
封裝： 12.70 X 12.70 MM, PLASTIC, FBGA-481
文件頁(yè)數(shù)： 41/66頁(yè)
文件大?。?/td> 3663K
代理商： MC-10118BF1-ENY-A
MC-10118B
Data Sheet R19DS0008EJ0700
44
2.5.5
IIC interface
(IO buffer drive capability: 2 mA)
Standard ModeNote 1
High-Speed ModeNote 1
Parameter
Symbol
Conditions
MIN.
MAX.
MIN.
MAX.
Unit
IIC_SCL clock frequency
fC
0
70
0
341
kHz
IIC bus free time
tBF
Interval between stop and start
conditions
4.7
1.3
s
IIC hold timeNote 2
tH1
4.0
0.6
s
tWL
“Low” state
4.7
1.3
s
IIC hold time (SCL clock)
tWH
“Hi” state
4.0
0.6
s
IIC setup time
tSU1
Start condition
Restart condition
4.7
0.6
s
IIC data setup time
tSU2
250
100Note 3
ns
IIC rise time
tR
SDA and SCL signals
300Note 4
ns
IIC fall time
tF
SDA and SCL signals
300Note 4
ns
IIC setup time
tSU3
Stop condition
4.0
0.6
s
Clock fall output
5.0
s
IIC data hold time
tH2
Clock fall input
0
3.45
0Note 5
0.9Note 6
s
Capacitance load of each
IIC bus line
Cb
400
400
p
F
Notes 1.
Select the standard mode or high-speed mode by using the SMC0 bit of the IIC0 clock select register
(IICCL0).
2.
At the start condition, the first clock pulse is generated after the hold time.
3.
The high-speed mode I
2C bus can be used in the standard-mode I2C bus system. In this case, set the
high-speed mode I
2C bus so that it meets the following conditions.
If the system does not extend the IIC_SCL signal’s low state hold time: tSU2 250 ns
4.
Do not input noise exceeding the hysteresis width of the 1.8 V system IO Schmitt buffer during a rise or
fall time.
5.
The system requires a minimum of 300 ns hold time internally for the SDA signal (at VIH (MIN.) [0.7 VDD2]
of IIC_SCL signal) in order to occupy the undefined area at the falling edge of IIC_SCL.
6.
If the system does not extend the IIC_SCL signal low hold time (tWL), only the maximum data hold time
(tH2) needs to be satisfied.
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