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參數(shù)資料
| 型號： | MC-10118BF1-ENY-A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA481 |
| 封裝： | 12.70 X 12.70 MM, PLASTIC, FBGA-481 |
| 文件頁數(shù)： | 35/66頁 |
| 文件大?。?/td> | 3663K |
| 代理商： | MC-10118BF1-ENY-A |
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MC-10118B
Data Sheet R19DS0008EJ0700
38
(2) Reset (A_RESETB)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
A_RESETB low-level width
tA_RESETB
6
ms
Remark
In the case of a hardware reset.
Figure 2-4. Reset Timing
A_RESETB
tRSTIB, tA_RESETB
(3) Power supply start-up Timing (without power supply -> Normal)
DET1
A_RESETB
(inside PLL)
C32K
Min:200us
Core power supply (V)
PLL power supply (VA1/2/3)
IO power supply (VIO18)
Time when a VIO3 power supply becomes stable.
(1)
(2)
(3)
(4)
Min:200us
(5)
IO power supply (VIO3)
(6)
Time when a VIO18 power supply becomes stable.
Min:0us
Time when V,VA1,VA2,VA3 power supply becomes stable.
Figure 2-5. Power supply start-up timing
Remarks “Stable” means that each power supply becomes the specification minimum voltage.
The timing figure which starts from the “Without power supply”.
(1) IO power supply (VIO18) is supplied, and stands by until a power supply becomes stable.
(2) IO power supply (VIO3) is supplied, and stands by until a power supply becomes stable.
(3) Corepower supply (V) and PLL power supply (VA1/2/3) are supplied, and stands by until a power supply becomes
stable.
(4) RTC clock 32.768kHz (C32K) is input.
(5) DET1 is signal is started.
(6) A_RESETB signal rising (reset release), and PLL begins to oscillate.
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