參數(shù)資料
型號： MC-10118BF1-ENY-A
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA481
封裝： 12.70 X 12.70 MM, PLASTIC, FBGA-481
文件頁數(shù)： 10/66頁
文件大?。?/td> 3663K
代理商： MC-10118BF1-ENY-A
MC-10118B
Data Sheet R19DS0008EJ0700
16
(6) SPI interface signals (VIO3)
Pin Name
Pin No.
I/O
Function
Alternate Pin
Function
Type
Handling When
Not Used
SP0_CLK
B8
I/O
SPI0 clock output
MWI_SK
D
Leave open.
SP0_SI
C8
Input
SPI0 data
MWI_SI
D
Leave open.
SP0_SO
D8
Output
SPI0 data
MWI_SO
D
Leave open.
SP0_CS0
E9
I/O
SPI0 chip select
MWI_CS
D
Leave open.
SP0_CS[2:1]
E8, H8
Output
SPI0 chip select
GIO_P[49:48]
D
Leave open.
SP1_CLK
H2
I/O
SPI1 clock input
GIO_P73
NTS_VS
D
Leave open.
SP1_SI
H3
Input
SPI1 data
GIO_P74
NTS_HS
D
Leave open.
SP1_SO
H4
Output
SPI1 data
GIO_P75
NTS_DATA0
CAM_YUV0
D
Leave open.
SP1_CS5
J5
Output
SPI1 chip select
GIO_P81
NTS_DATA6
PM1_SI
D
Leave open.
SP1_CS4
H5
Output
SPI1 chip select
GIO_P80
NTS_DATA5
PM1_SEN
D
Leave open.
SP1_CS[3:1]
J4, J3, J2 Output
SPI1 chip select
GIO_P[79:77]
NTS_DATA[4:2]
CAM_YUV[4:2]
D
Leave open.
SP1_CS0
J1
I/O
SPI1 chip select
GIO_P76
NTS_DATA1
CAM_YUV1
D
Leave open.
SP2_CLK
D1
I/O
SPI2 clock input
DTV_BCLK
C
Leave open.
SP2_SI
C2
Input
SPI2 data
DTV_DATA
D
Leave open.
SP2_SO
D2
Output
SPI2 data
DTV_PSYNC
D
Leave open.
SP2_CS0
D3
I/O
SPI2 chip select
DTV_VLD
D
Leave open.
(7) Terrestrial digital TV interface signals (VIO3)
Pin Name
Pin No.
I/O
Function
Alternate Pin
Function
Type
Handling When
Not Used
DTV_BCLK
D1
Input
Clock
SP2_CLK
C
Leave open.
DTV_DATA
C2
Input
YUV data
SP2_SI
D
Leave open.
DTV_PSYNC
D2
Input
Vertical synchronization
SP2_SO
D
Leave open.
DTV_VLD
D3
Input
Horizontal synchronization
SP2_CS0
D
Leave open.
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