參數(shù)資料
型號(hào)： MC-10118BF1-ENY-A
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA481
封裝： 12.70 X 12.70 MM, PLASTIC, FBGA-481
文件頁(yè)數(shù)： 38/66頁(yè)
文件大小： 3663K
代理商： MC-10118BF1-ENY-A
MC-10118B
Data Sheet R19DS0008EJ0700
41
2.5.3
Asynchronous bus (AB0) interface
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Asynchronous single
read access time
t201
Note
(1 + T0 + T1 + T2)
Tf 3
(2 + T0 + T1 + T2)
Tf + 3
ns
CSZ rise to ADVZ fall
t202
Note
Tf
3
2Tf + 3
ns
ADVZ active width
t203
AB0_ADVZ = Low
Tf
3
Tf + 3
ns
Lower ADD for ADMUX
hold time
t204
T0
Tf 3
T0
Tf + 3
ns
Delay time from ADVZ
rise to read signal output
t205
Falling edge of AB0_RDZ
T0
Tf 3
T0
Tf + 3
ns
Read signal active width
t206
AB0_RDZ = Low
T1
Tf 3
T1
Tf + 3
ns
Delay time from RDZ rise
to CSZ fall output
t207
Rising edge of AB0_RDZ
T2
Tf 3
T2
Tf + 3
ns
CS assert interval time
t208
CSInt
Tf 3
ns
Asynchronous _RDATA
setup time
t209
Rising edge of AB0_RDZ
15
ns
Asynchronous _RDATA
hold time
t210
Rising edge of AB0_RDZ
0
ns
Delay time from address
determination to RDZ fall
t211
Falling edge of AB0_RDZNote
(1 + T0)
Tf 8
ns
Delay time from CSZ fall
to RDZ rise output
t212
Falling edge of AB0_RDZNote
(1 + T0)
Tf 3
ns
Asynchronous single
write access time
t220
Note
(1 + T0 + T1W +
T2W)
Tf 3
(2 + T0 + T1W +
T2W)
Tf + 3
ns
Delay time from ADVZ
rise to write signal output
t221
Rising edge of AB0_WRZ
T0×Tf
3
T0
Tf + 3
ns
Write signal active width
t222
AB0_WRZ = Low
T1W
Tf 3
T1W
Tf + 3
ns
Delay time from WRZ
rise to CSZ fall output
t223
Rising edge of AB0_WRZ
T2W
Tf 3
T2W
Tf + 3
ns
Asynchronous _WDATA
output hold time
t224
Rising edge of AB0_WRZ
T2W
Tf 8
ns
Delay time from address
determination to WRZ
fall
t225
Falling edge of AB0_WRZNote
(1 + T0)
Tf 8
ns
Delay time from CSZ fall
to WRZ fall output
t226
Falling edge of AB0_WRZNote
(1 + T0)
Tf 3
ns
Note
The time from the CSB falling edge to the ADV falling edge (Tf) can be shortened by setting a register.
Remark
Tf = 1/4 of AB0_CLK. (When frequency ratio 1/4 is usually the time of the state (AB0_CLK:FLASH_CLK
= 2:1).
T0, T1, T2, CSInt: Values set to read the wait timing control register (AB0_CSxWAITCTRL)
T1W, T2W: Values set to write the wait timing control register (AB0_CSxWAITCTRL_W)
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