參數(shù)資料
型號: MBM30LV0128-PFTR
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: 128 M (16 M X 8) BIT NAND-type
中文描述: 16M X 8 FLASH 2.7V PROM, PDSO48
封裝: PLASTIC, REVERSE, TSOP-48
文件頁數(shù): 24/43頁
文件大小: 397K
代理商: MBM30LV0128-PFTR
MBM30LV0064
24
01h
D
OUT
D
OUT
D
OUT
t
CLS
t
CLH
t
CS
t
CH
t
ALS
t
ALH
t
DS
t
DH
t
DS
t
DH
A
17
to
A
22
A
9
to
A
16
A
0
to
A
7
t
ALH
t
WB
t
R
t
AR2
t
RC
t
RR
t
REA
256 + M 256 + M + 1
**: SE = GND input : D
OUT
527
= V
CC
input : D
OUT
511
Note: The CE signal must stay “Low” after the third address input and during Busy state.
Column address
M
**
CLE
CE
WE
ALE
I/O0
to I/O7
R/B
RE
: V
IH
or V
IL
Figure 16 Read Cycle (2) Timing Diagram
50h
D
OUT
D
OUT
D
OUT
t
CLS
t
CLH
t
CS
t
CH
t
ALS
t
ALH
t
DS
t
DH
t
DS
t
DH
A
17
to
A
22
A
9
to
A
16
A
0
to
A
7
t
ALH
t
WB
t
R
t
AR2
t
RC
t
RR
t
REA
512 + M 512 + M + 1
**: SE = GND input : D
OUT
527
= Do not input V
CC
Column address
M
**
CLE
CE
WE
ALE
I/O0
to I/O7
R/B
RE
: V
IH
or V
IL
527
Figure 17 Read Cycle (3) Timing Diagram
Note: The CE signal must stay “Low” after the third address input and during Busy state.
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